Inventor · disambiguated record
Usha Raghuram
Also filed as: RAGHURAM USHA
32 granted patents·7 pending applications·888 citations·filing 1997–2024
97Inventor score
Files withSANDISK 3D LLC14CYPRESS SEMICONDUCTOR CORP4RAGHURAM USHA3GLOBALFOUNDRIES INC2INTERMOLECULAR INC2
Top patents by PatentIndex Score
39 records- 0199US7915164B2Method for forming doped polysilicon via connecting polysilicon layersSANDISK 3D LLC·Filed 2010·Granted Mar 29, 2011·251 cites·7 claims
- 0298US7575984B2Conductive hard mask to protect patterned features during trench etchSANDISK 3D LLC·Filed 2006·Granted Aug 18, 2009·111 cites·17 claims
- 0398US7566974B2Doped polysilicon via connecting polysilicon layersSANDISK 3D LLC·Filed 2004·Granted Jul 28, 2009·190 cites·17 claims
- 0497US7728318B2Nonvolatile phase change memory cell having a reduced contact areaSANDISK CORP·Filed 2006·Granted Jun 1, 2010·83 cites·18 claims
- 0594US7517796B2Method for patterning submicron pillarsSANDISK 3D LLC·Filed 2005·Granted Apr 14, 2009·22 cites·21 claims
- 0693US9105497B2Methods of forming gate structures for transistor devices for CMOS applicationsGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 11, 2015·19 cites·24 claims
- 0793US7307013B2Nonselective unpatterned etchback to expose buried patterned featuresSANDISK 3D LLC·Filed 2004·Granted Dec 11, 2007·67 cites·91 claims
- 0892US9362283B2Gate structures for transistor devices for CMOS applications and productsGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 7, 2016·9 cites·20 claims
- 0992US7906392B2Pillar devices and methods of making thereofSANDISK 3D LLC·Filed 2008·Granted Mar 15, 2011·21 cites·3 claims
- 1091US7422985B2Method for reducing dielectric overetch using a dielectric etch stop at a planar surfaceSANDISK 3D LLC·Filed 2005·Granted Sep 9, 2008·16 cites·32 claims
- 1190US8987119B2Pillar devices and methods of making thereofDUNTON VANCE·Filed 2011·Granted Mar 24, 2015·15 cites·35 claims
- 1289US7846782B2Diode array and method of making thereofSANDISK 3D LLC·Filed 2007·Granted Dec 7, 2010·13 cites·12 claims
- 1388US8008187B2Method for reducing dielectric overetch using a dielectric etch stop at a planar surfaceSANDISK 3D LLC·Filed 2010·Granted Aug 30, 2011·7 cites·23 claims
- 1486US8298931B2Dual damascene with amorphous carbon for 3D deep via/trench applicationRAGHURAM USHA·Filed 2007·Granted Oct 30, 2012·12 cites·22 claims
- 1577US9297775B2Combinatorial screening of metallic diffusion barriersINTERMOLECULAR INC·Filed 2014·Granted Mar 29, 2016·1 cites·20 claims
- 1677US8735302B2High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extractionJOSHI AMOL·Filed 2012·Granted May 27, 2014·4 cites·20 claims
- 1775US8163593B2Method of making a nonvolatile phase change memory cell having a reduced contact areaRAGHURAM USHA·Filed 2006·Granted Apr 24, 2012·8 cites·20 claims
- 1874US7915163B2Method for forming doped polysilicon via connecting polysilicon layersSANDISK 3D LLC·Filed 2009·Granted Mar 29, 2011·4 cites·13 claims
- 1968US7955515B2Method of plasma etching transition metal oxidesSANDISK 3D LLC·Filed 2007·Granted Jun 7, 2011·2 cites·11 claims
- 2066US8084366B2Modified DARC stack for resist patterningCHAN MICHAEL·Filed 2008·Granted Dec 27, 2011·2 cites·30 claims
- 2165US6406640B1Plasma etching methodCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Jun 18, 2002·9 cites·14 claims
- 2262US7790607B2Method for reducing dielectric overetch using a dielectric etch stop at a planar surfaceSANDISK 3D LLC·Filed 2007·Granted Sep 7, 2010·1 cites·37 claims
- 2361US2024260275A1Fabrication method for a three-dimensional memory array of thin-film ferroelectric transistors using high-aspect-ratio local word line damascene processSUNRISE MEMORY CORP·Filed 2024·Application pending·0 cites
- 2459US8854067B2Circular transmission line methods compatible with combinatorial processing of semiconductorsJOSHI AMOL·Filed 2012·Granted Oct 7, 2014·1 cites·12 claims
- 2558US2024114689A1Fabrication method for a three-dimensional memory array of thin-film ferroelectric transistors formed with an oxide semiconductor channelSUNRISE MEMORY CORP·Filed 2023·Application pending·0 cites
- 2657US8071475B2Liner for tungsten/silicon dioxide interface in memoryTANAKA YOICHIRO·Filed 2007·Granted Dec 6, 2011·1 cites·25 claims
- 2756US8759176B2Patterning of submicron pillars in a memory arrayRAGHURAM USHA·Filed 2009·Granted Jun 24, 2014·0 cites·21 claims
- 2856US6756315B1Method of forming contact openingsCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Jun 29, 2004·7 cites·25 claims
- 2955US8722518B2Methods for protecting patterned features during trench etchSANDISK 3D LLC·Filed 2013·Granted May 13, 2014·0 cites·17 claims
- 3054US2009273022A1Conductive hard mask to protect patterned features during trench etchSANDISK 3D LLC·Filed 2009·Application pending·0 cites
- 3153US8859431B2Process to remove Ni and Pt residues for NiPtSi application using chlorine gasINTERMOLECULAR INC·Filed 2013·Granted Oct 14, 2014·0 cites·20 claims
- 3251US2011306177A1Method for reducing dielectric overetch using a dielectric etch stop at a planar surfaceDUNTON SAMUEL V·Filed 2011·Application pending·0 cites
- 3349US8466058B2Process to remove Ni and Pt residues for NiPtSi applications using chlorine gasDUONG ANH·Filed 2011·Granted Jun 18, 2013·0 cites·17 claims
- 3447US6165375APlasma etching methodCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Dec 26, 2000·12 cites·15 claims
- 3547US2012200852A1Spectroscopy and spectral imaging methods and apparatusTEJADA FRANCISCO·Filed 2011·Application pending·0 cites
- 3645US8268678B2Diode array and method of making thereofMAXWELL STEVEN·Filed 2010·Granted Sep 18, 2012·0 cites·5 claims
- 3742US2007010100A1Method of plasma etching transition metals and their compoundsMATRIX SEMICONDUCTOR INC·Filed 2005·Application pending·0 cites
- 3830US2012091550A1Spectroscopy and spectral imaging methods and apparatusMORGAN RICKY JAMES·Filed 2011·Application pending·0 cites
- 3929US6890860B1Method for etching and/or patterning a silicon-containing layerCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted May 10, 2005·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →