Inventor · disambiguated record
Uwe Schroeder
Also filed as: SCHROEDER UWE · SCHROEDER UWE P · SCHROEDER UWE PAUL
58 granted patents·12 pending applications·839 citations·filing 1996–2018
99Inventor score
Files withINFINEON TECHNOLOGIES AG29IBM10GLOBALFOUNDRIES INC9SCHROEDER UWE PAUL5INFINEON TECHNOLOGIES CORP3
Top patents by PatentIndex Score
70 records- 0194US6498061B2Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formationIBM·Filed 2000·Granted Dec 24, 2002·66 cites·11 claims
- 0294US6399490B1Highly conformal titanium nitride deposition process for high aspect ratio structuresIBM·Filed 2000·Granted Jun 4, 2002·104 cites·22 claims
- 0391US9437420B2Capacitors including amorphous dielectric layers and methods of forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Sep 6, 2016·10 cites·20 claims
- 0489US7985676B2Method of making a contact in a semiconductor deviceINFINEON TECHNOLOGIES AG·Filed 2010·Granted Jul 26, 2011·10 cites·22 claims
- 0589US6451662B1Method of forming low-leakage on-chip capacitorIBM·Filed 2001·Granted Sep 17, 2002·47 cites·3 claims
- 0688US9547741B2Methods, apparatus, and system for using filler cells in design of integrated circuit devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 17, 2017·12 cites·19 claims
- 0788US7723771B2Zirconium oxide based capacitor and process to manufacture the sameQIMONDA AG·Filed 2007·Granted May 25, 2010·17 cites·36 claims
- 0888US7666752B2Deposition method for a transition-metal-containing dielectricQIMONDA AG·Filed 2007·Granted Feb 23, 2010·17 cites·9 claims
- 0987US6426253B1Method of forming a vertically oriented device in an integrated circuitINFINEON TECHNOLOGIES AG·Filed 2000·Granted Jul 30, 2002·49 cites·27 claims
- 1086US9245087B1Methods, apparatus and system for reduction of power consumption in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 26, 2016·8 cites·20 claims
- 1186US6403423B1Modified gate processing for optimized definition of array and logic devices on same chipIBM·Filed 2000·Granted Jun 11, 2002·38 cites·30 claims
- 1284US6605838B1Process flow for thick isolation collar with reduced lengthIBM·Filed 2002·Granted Aug 12, 2003·39 cites·20 claims
- 1382US6576550B1‘Via first’ dual damascene process for copper metallizationINFINEON TECHNOLOGIES CORP·Filed 2000·Granted Jun 10, 2003·39 cites·17 claims
- 1482US6335247B1Integrated circuit vertical trench device and method of forming thereofINFINEON TECHNOLOGIES AG·Filed 2000·Granted Jan 1, 2002·25 cites·19 claims
- 1581US6548357B2Modified gate processing for optimized definition of array and logic devices on same chipIBM·Filed 2002·Granted Apr 15, 2003·28 cites·18 claims
- 1680US6599798B2Method of preparing buried LOCOS collar in trench DRAMSINFINEON TECHNOLOGIES AG·Filed 2001·Granted Jul 29, 2003·26 cites·11 claims
- 1777US7678704B2Method of making a contact in a semiconductor deviceINFINEON TECHNOLOGIES AG·Filed 2005·Granted Mar 16, 2010·5 cites·26 claims
- 1877US6897943B2Method and apparatus for aerial image improvement in projection lithography using a phase shifting apertureINFINEON TECHNOLOGIES AG·Filed 2000·Granted May 24, 2005·20 cites·24 claims
- 1977US6620724B1Low resistivity deep trench fill for DRAM and EDRAM applicationsINFINEON TECHNOLOGIES AG·Filed 2002·Granted Sep 16, 2003·23 cites·38 claims
- 2075US7846616B2Lithography masks and methodsINFINEON TECHNOLOGIES AG·Filed 2005·Granted Dec 7, 2010·4 cites·29 claims
- 2175US6379869B1Method of improving the etch resistance of chemically amplified photoresists by introducing silicon after patterningINFINEON TECHNOLOGIES AG·Filed 1999·Granted Apr 30, 2002·36 cites·25 claims
- 2274US8153335B2Lithography masks, systems, and manufacturing methodsSCHROEDER UWE PAUL·Filed 2009·Granted Apr 10, 2012·3 cites·25 claims
- 2374US6740595B2Etch process for recessing polysilicon in trench structuresINFINEON TECHNOLOGIES AG·Filed 2002·Granted May 25, 2004·16 cites·8 claims
- 2473US8344438B2Electrode of an integrated circuitQIMONDA AG·Filed 2008·Granted Jan 1, 2013·6 cites·14 claims
- 2573US6486024B1Integrated circuit trench device with a dielectric collar stack, and method of forming thereofINFINEON TECHNOLOGIES AG·Filed 2000·Granted Nov 26, 2002·14 cites·20 claims
- 2670US8247845B2Electrostatic discharge (ESD) protection circuit placement in semiconductor devicesSCHROEDER UWE PAUL·Filed 2008·Granted Aug 21, 2012·5 cites·28 claims
- 2770US6605860B1Semiconductor structures and manufacturing methodsINFINEON TECHNOLOGIES AG·Filed 2000·Granted Aug 12, 2003·10 cites·2 claims
- 2869US6540938B1Liquid crystalline light-modulating deviceIBM·Filed 1996·Granted Apr 1, 2003·42 cites·4 claims
- 2968US7224030B2Method and apparatus for producing rectangular contact holes utilizing side lobe formationINFINEON TECHNOLOGIES AG·Filed 2004·Granted May 29, 2007·6 cites·24 claims
- 3067US6605396B2Resolution enhancement for alternating phase shift masksINFINEON TECHNOLOGIES AG·Filed 2001·Granted Aug 12, 2003·9 cites·31 claims
- 3166US7268080B2Method for printing contacts on a substrateINFINEON TECHNOLOGIES AG·Filed 2005·Granted Sep 11, 2007·3 cites·15 claims
- 3266US6355503B2Method for producing square contact holes utilizing side lobe formationINFINEON TECHNOLOGIES AG·Filed 2000·Granted Mar 12, 2002·6 cites·6 claims
- 3365US10248754B2Multi-stage pattern recognition in circuit designsGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 2, 2019·1 cites·20 claims
- 3465US7049241B2Method for forming a trench in a layer or a layer stack on a semiconductor waferINFINEON TECHNOLOGIES AG·Filed 2004·Granted May 23, 2006·9 cites·20 claims
- 3564US10276674B2Method of forming a gate contact structure and source/drain contact structure for a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 30, 2019·1 cites·20 claims
- 3664US7157371B2Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devicesINFINEON TECHNOLOGIES AG·Filed 2003·Granted Jan 2, 2007·9 cites·15 claims
- 3763US6767682B1Method for producing quadratic contact holes utilizing side lobe formationINFINEON TECHNOLOGIES AG·Filed 2000·Granted Jul 27, 2004·5 cites·10 claims
- 3861US7648805B2Masks and methods of manufacture thereofIBM·Filed 2006·Granted Jan 19, 2010·2 cites·23 claims
- 3959US9195142B2Lithography masks, systems, and manufacturing methodsINFINEON TECHNOLOGIES AG·Filed 2013·Granted Nov 24, 2015·0 cites·20 claims
- 4059US7074528B2Effective assist pattern for nested and isolated contactsINFINEON TECHNOLOGIES AG·Filed 2003·Granted Jul 11, 2006·5 cites·30 claims
- 4158US7859645B2Masks and methods of manufacture thereofINFINEON TECHNOLOGIES AG·Filed 2009·Granted Dec 28, 2010·0 cites·20 claims
- 4258US6613642B2Method for surface roughness enhancement in semiconductor capacitor manufacturingIBM·Filed 2001·Granted Sep 2, 2003·8 cites·18 claims
- 4357US6740555B1Semiconductor structures and manufacturing methodsINFINEON TECHNOLOGIES AG·Filed 1999·Granted May 25, 2004·16 cites·7 claims
- 4456US7939137B2Method and device for producing parts having a sealing layer on the surface, and corresponding partsKLEBCHEMIE M G BECKER GMBH·Filed 2002·Granted May 10, 2011·2 cites·18 claims
- 4556US7157194B2Method for exposing a substrate with a structure pattern which compensates for the optical proximity effectINFINEON TECHNOLOGIES AG·Filed 2004·Granted Jan 2, 2007·4 cites·6 claims
- 4655US6316168B1Top layer imaging lithography for semiconductor processingSIEMENS AG·Filed 1999·Granted Nov 13, 2001·19 cites·20 claims
- 4754US8663877B2Lithography masks, systems, and manufacturing methodsSCHROEDER UWE PAUL·Filed 2012·Granted Mar 4, 2014·0 cites·24 claims
- 4851US6559002B1Rough oxide hard mask for DT surface area enhancement for DT DRAMINFINEON TECHNOLOGIES CORP·Filed 2001·Granted May 6, 2003·3 cites·10 claims
- 4949US2016099239A1Methods, apparatus and system for reduction of power consumption in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 5048US8003305B2Method for patterning a semiconductor waferIBM·Filed 2008·Granted Aug 23, 2011·0 cites·25 claims
Showing the top 50 of 70 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →