Inventor · disambiguated record
Valli Arunachalam
Also filed as: ARUNACHALAM VALLI
6 granted patents·3 pending applications·60 citations·filing 1999–2012
83Inventor score
Top patents by PatentIndex Score
9 records- 0191US8778789B2Methods for fabricating integrated circuits having low resistance metal gate structuresGLOBALFOUNDRIES INC·Filed 2012·Granted Jul 15, 2014·13 cites·20 claims
- 0284US9142633B2Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structuresGLOBALFOUNDRIES INC·Filed 2012·Granted Sep 22, 2015·7 cites·17 claims
- 0379US8691689B1Methods for fabricating integrated circuits having low resistance device contactsGLOBALFOUNDRIES INC·Filed 2012·Granted Apr 8, 2014·5 cites·20 claims
- 0475US6500315B1Method and apparatus for forming a layer on a substrateMOTOROLA INC·Filed 2000·Granted Dec 31, 2002·15 cites·23 claims
- 0557US6139696AMethod and apparatus for forming a layer on a substrateMOTOROLA INC·Filed 1999·Granted Oct 31, 2000·18 cites·2 claims
- 0655US8211794B2Properties of metallic copper diffusion barriers through silicon surface treatmentsARUNACHALAM VALLI·Filed 2007·Granted Jul 3, 2012·2 cites·21 claims
- 0745US2009127594A1MOS TRANSISTORS HAVING NiPtSi CONTACT LAYERS AND METHODS FOR FABRICATING THE SAMEADVANCED MICRO DEVICES INC·Filed 2007·Application pending·0 cites
- 0836US2004087163A1Method for forming magnetic clad bit lineFiled 2002·Application pending·0 cites
- 0934US2011204518A1Scalability with reduced contact resistanceGLOBALFOUNDRIES INC·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →