Inventor · disambiguated record
Vassilios Gerousis
Also filed as: GEROUSIS VASSILIOS · GEROUSIS VASSILIOS C · GEROUSIS VASSILIOS CONSTANTINOS
22 granted patents·2 pending applications·441 citations·filing 2007–2024
95Inventor score
Files withSAMSUNG ELECTRONICS CO LTD10CADENCE DESIGN SYSTEMS INC4CHANG HONGLIANG3ZHANG LIZHENG2CADENCE DESIGN SYSTEM INC1
Top patents by PatentIndex Score
24 records- 0196US10886224B2Power distribution network using buried power railSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Jan 5, 2021·17 cites·18 claims
- 0295US8336010B1Design-specific on chip variation de-rating factors for static timing analysis of integrated circuitsCHANG HONGLIANG·Filed 2010·Granted Dec 18, 2012·202 cites·20 claims
- 0394US10811415B2Semiconductor device and method for making the sameSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Oct 20, 2020·10 cites·20 claims
- 0493US8782586B2Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterningSEZGINER ABDURRAHMAN·Filed 2009·Granted Jul 15, 2014·51 cites·24 claims
- 0592US9087174B1Methods, systems, and articles of manufacture for implementing multiple-patterning-aware design rule check for electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jul 21, 2015·20 cites·32 claims
- 0692US8782570B1Methods, systems, and articles of manufacture for implementing a physical electronic circuit design with multiple-patterning techniquesLI JIANMIN·Filed 2012·Granted Jul 15, 2014·28 cites·34 claims
- 0791US8863048B1Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic designCADENCE DESIGN SYSTEM INC·Filed 2013·Granted Oct 14, 2014·22 cites·32 claims
- 0890US8086978B2Method and system for performing statistical leakage characterization, analysis, and modelingZHANG LIZHENG·Filed 2008·Granted Dec 27, 2011·32 cites·36 claims
- 0989US10510774B2Integrated circuit power distribution networkIMEC VZW·Filed 2017·Granted Dec 17, 2019·13 cites·19 claims
- 1089US10192018B1Method and system for implementing efficient trim data representation for an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 29, 2019·10 cites·23 claims
- 1184US11552067B2Semiconductor cell blocks having non-integer multiple of cell heightsSAMSUNG ELECTRONICS CO LTD·Filed 2020·Granted Jan 10, 2023·2 cites·7 claims
- 1283US9286432B1Methods, systems, and articles of manufacture for implementing correct-by-construction physical designs with multiple-patterning-awarenessCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Mar 15, 2016·8 cites·31 claims
- 1380US8762908B1Static timing analysis with design-specific on chip variation de-rating factorsCHANG HONGLIANG·Filed 2010·Granted Jun 24, 2014·7 cites·26 claims
- 1479US9245076B2Orthogonal circuit element routingIBM·Filed 2013·Granted Jan 26, 2016·5 cites·20 claims
- 1576US8151229B1System and method of computing pin criticalities under process variations for timing analysis and optimizationCHANG HONGLIANG·Filed 2007·Granted Apr 3, 2012·9 cites·23 claims
- 1673US2024379653A1Semiconductor cell blocks having non-integer multiple of cell heightsSAMSUNG ELECTRONICS CO LTD·Filed 2024·Application pending·0 cites
- 1771US11158738B2Method of forming isolation dielectrics for stacked field effect transistors (FETs)SAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Oct 26, 2021·1 cites·14 claims
- 1870US12080703B2Semiconductor cell blocks having non-integer multiple of cell heightsSAMSUNG ELECTRONICS CO LTD·Filed 2022·Granted Sep 3, 2024·0 cites·14 claims
- 1967US11605574B2Method of forming a thermal shield in a monolithic 3-d integrated circuitSAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted Mar 14, 2023·0 cites·19 claims
- 2066US8069432B2Method and system for performing statistical leakage characterization, analysis, and modelingZHANG LIZHENG·Filed 2008·Granted Nov 29, 2011·4 cites·22 claims
- 2159US10971420B2Method of forming a thermal shield in a monolithic 3-D integrated circuitSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Apr 6, 2021·0 cites·14 claims
- 2250US11189600B2Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bondingSAMSUNG ELECTRONICS CO LTD·Filed 2020·Granted Nov 30, 2021·0 cites·19 claims
- 2350US9767245B1Method, system, and computer program product for improving mask designs and manufacturability of electronic designs for multi-exposure lithographyCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Sep 19, 2017·0 cites·28 claims
- 2441US2020201954A1Method of designing a layout for a semiconductor integrated circuitSAMSUNG ELECTRONICS CO LTD·Filed 2019·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →