Inventor · disambiguated record
Venkateswara Madduri
Also filed as: MADDURI VENKATESWARA · MADDURI VENKATESWARA R · MADDURI VENKATESWARA RAO
57 granted patents·30 pending applications·639 citations·filing 1997–2023
98Inventor score
Files withINTEL CORP72ADVANCED MICRO DEVICES INC7MADDURI VENKATESWARA R4KOEBERL PATRICK1MADDURI VENKATESWARA1
Top patents by PatentIndex Score
87 records- 0199US10224954B1Floating point to fixed point conversionINTEL CORP·Filed 2017·Granted Mar 5, 2019·48 cites·20 claims
- 0298US10656942B2Fixed point to floating point conversionINTEL CORP·Filed 2019·Granted May 19, 2020·29 cites·25 claims
- 0394US11256504B2Apparatus and method for complex by complex conjugate multiplicationINTEL CORP·Filed 2017·Granted Feb 22, 2022·11 cites·26 claims
- 0493US10223114B1Fixed point to floating point conversionINTEL CORP·Filed 2017·Granted Mar 5, 2019·8 cites·25 claims
- 0593US7640417B2Instruction length decoderINTEL CORP·Filed 2007·Granted Dec 29, 2009·28 cites·23 claims
- 0692US10705839B2Apparatus and method for multiplying, summing, and accumulating sets of packed bytesINTEL CORP·Filed 2017·Granted Jul 7, 2020·9 cites·21 claims
- 0789US11074073B2Apparatus and method for multiply, add/subtract, and accumulate of packed data elementsINTEL CORP·Filed 2017·Granted Jul 27, 2021·5 cites·12 claims
- 0889US10664270B2Apparatus and method for vector multiply and accumulate of unsigned doublewordsINTEL CORP·Filed 2017·Granted May 26, 2020·6 cites·21 claims
- 0987US6189140B1Debug interface including logic generating handshake signals between a processor, an input/output port, and a trace logicADVANCED MICRO DEVICES INC·Filed 1998·Granted Feb 13, 2001·138 cites·16 claims
- 1085US8930678B2Instruction and logic to length decode X86 instructionsMADDURI VENKATESWARA R·Filed 2012·Granted Jan 6, 2015·11 cites·24 claims
- 1181US12393422B2Apparatus and method for vector packed signed/unsigned shift, round, and saturateINTEL CORP·Filed 2021·Granted Aug 19, 2025·1 cites·21 claims
- 1281US10514924B2Apparatus and method for performing dual signed and unsigned multiplication of packed data elementsINTEL CORP·Filed 2017·Granted Dec 24, 2019·2 cites·21 claims
- 1380US10763891B2Floating point to fixed point conversionINTEL CORP·Filed 2019·Granted Sep 1, 2020·3 cites·20 claims
- 1480US6142683ADebug interface including data steering between a processor, an input/output port, and a trace logicADVANCED MICRO DEVICES INC·Filed 1998·Granted Nov 7, 2000·92 cites·23 claims
- 1579US11163563B2Systems, apparatuses, and methods for dual complex multiply add of signed wordsINTEL CORP·Filed 2017·Granted Nov 2, 2021·2 cites·20 claims
- 1679US11036499B2Systems, apparatuses, and methods for controllable sine and/or cosine operationsINTEL CORP·Filed 2017·Granted Jun 15, 2021·2 cites·20 claims
- 1778US11243765B2Apparatus and method for scaling pre-scaled results of complex multiply-accumulate operations on packed real and imaginary data elementsINTEL CORP·Filed 2017·Granted Feb 8, 2022·2 cites·33 claims
- 1878US9454371B2Micro-architecture for eliminating MOV operationsMADDURI VENKATESWARA·Filed 2012·Granted Sep 27, 2016·7 cites·25 claims
- 1977US6145100ADebug interface including timing synchronization logicADVANCED MICRO DEVICES INC·Filed 1998·Granted Nov 7, 2000·74 cites·16 claims
- 2076US10417001B2Physical register table for eliminating move instructionsINTEL CORP·Filed 2012·Granted Sep 17, 2019·4 cites·15 claims
- 2175US6154856ADebug interface including state machines for timing synchronization and communicationADVANCED MICRO DEVICES INC·Filed 1998·Granted Nov 28, 2000·75 cites·35 claims
- 2274US7305542B2Instruction length decoderINTEL CORP·Filed 2002·Granted Dec 4, 2007·16 cites·21 claims
- 2373US9710277B2Processor power management based on class and content of instructionsMADDURI VENKATESWARA R·Filed 2010·Granted Jul 18, 2017·4 cites·15 claims
- 2471US10318298B2Apparatus and method for shifting quadwords and extracting packed wordsINTEL CORP·Filed 2017·Granted Jun 11, 2019·1 cites·24 claims
- 2570US11573799B2Apparatus and method for performing dual signed and unsigned multiplication of packed data elementsINTEL CORP·Filed 2021·Granted Feb 7, 2023·0 cites·25 claims
- 2670US11294679B2Apparatus and method for multiplication and accumulation of complex valuesINTEL CORP·Filed 2017·Granted Apr 5, 2022·1 cites·22 claims
- 2770US10552154B2Apparatus and method for multiplication and accumulation of complex and real packed data elementsINTEL CORP·Filed 2017·Granted Feb 4, 2020·1 cites·27 claims
- 2870US10514923B2Apparatus and method for vector multiply and accumulate of signed doublewordsINTEL CORP·Filed 2017·Granted Dec 24, 2019·1 cites·21 claims
- 2969US11704124B2Instructions for vector multiplication of unsigned words with roundingINTEL CORP·Filed 2022·Granted Jul 18, 2023·0 cites·23 claims
- 3069US10496573B2Context-sensitive interruptsINTEL CORP·Filed 2017·Granted Dec 3, 2019·1 cites·25 claims
- 3167US6085311AInstruction alignment unit employing dual instruction queues for high frequency instruction dispatchADVANCED MICRO DEVICES INC·Filed 1999·Granted Jul 4, 2000·38 cites·25 claims
- 3265US11755323B2Apparatus and method for complex by complex conjugate multiplicationINTEL CORP·Filed 2022·Granted Sep 12, 2023·0 cites·24 claims
- 3365US11656870B2Systems, apparatuses, and methods for dual complex multiply add of signed wordsINTEL CORP·Filed 2021·Granted May 23, 2023·0 cites·15 claims
- 3465US11579871B2Systems, apparatuses, and methods for controllable sine and/or cosine operationsINTEL CORP·Filed 2021·Granted Feb 14, 2023·0 cites·30 claims
- 3565US10977039B2Apparatus and method for performing dual signed and unsigned multiplication of packed data elementsINTEL CORP·Filed 2019·Granted Apr 13, 2021·0 cites·25 claims
- 3665US2022236991A1Apparatus and method for vector horizontal add of signed/unsigned words and doublewordsINTEL CORP·Filed 2022·Application pending·0 cites
- 3764US2022129273A1Apparatus and method for vector multiply and subtraction of signed doublewordsINTEL CORP·Filed 2021·Application pending·0 cites
- 3864US2022129267A1Apparatus and method for right shifting packed quadwords and extracting packed doublewordsINTEL CORP·Filed 2021·Application pending·0 cites
- 3964US2022326946A1Apparatus and method for scaling pre-scaled results of complex mutiply-accumulate operations on packed real and imaginary data elementsINTEL CORP·Filed 2022·Application pending·0 cites
- 4064US2022129268A1Apparatus and method for right-shifting packed quadwords and extracting packed wordsINTEL CORP·Filed 2021·Application pending·0 cites
- 4163US2021357215A1Apparatus and method for multiply, add/subtract, and accumulate of packed data elementsINTEL CORP·Filed 2021·Application pending·0 cites
- 4262US11809867B2Apparatus and method for performing dual signed and unsigned multiplication of packed data elementsINTEL CORP·Filed 2020·Granted Nov 7, 2023·0 cites·24 claims
- 4362US10671547B2Lightweight trusted tasksKOEBERL PATRICK·Filed 2016·Granted Jun 2, 2020·1 cites·16 claims
- 4461US12346695B2Copy a subset of status flags from a control and status register to a flags registerINTEL CORP·Filed 2021·Granted Jul 1, 2025·0 cites·14 claims
- 4557US12204903B2Dual sum of quadword 16×16 multiply and accumulateINTEL CORP·Filed 2021·Granted Jan 21, 2025·0 cites·20 claims
- 4657US11221849B2Instructions for vector multiplication of unsigned words with roundingINTEL CORP·Filed 2017·Granted Jan 11, 2022·0 cites·23 claims
- 4756US10802826B2Apparatus and method for performing dual signed and unsigned multiplication of packed data elementsINTEL CORP·Filed 2017·Granted Oct 13, 2020·0 cites·24 claims
- 4855US11249754B2Apparatus and method for vector horizontal add of signed/unsigned words and doublewordsINTEL CORP·Filed 2017·Granted Feb 15, 2022·0 cites·24 claims
- 4954US2019196829A1Apparatus and method for vector multiply and subtraction of signed doublewordsOULD AHMED VALL ELMOUSTAPHA·Filed 2017·Application pending·0 cites
- 5054US2019196821A1Apparatus and method for right-shifting packed quadwords and extracting packed wordsINTEL CORP·Filed 2017·Application pending·0 cites
Showing the top 50 of 87 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →