Inventor · disambiguated record
Venkata N. S. N. Rao
Also filed as: RAO VENKATA N · RAO VENKATA N S N
23 granted patents·2 pending applications·144 citations·filing 2000–2019
94Inventor score
Top patents by PatentIndex Score
25 records- 0195US10061340B1Bandgap reference voltage generatorINVECAS INC·Filed 2018·Granted Aug 28, 2018·53 cites·19 claims
- 0290US8669792B2Voltage mode driver using pre-emphasis and de-emphasis signalsRAO VENKATA N S N·Filed 2012·Granted Mar 11, 2014·21 cites·20 claims
- 0389US10498564B2Receiver for handling high speed transmissionsINVECAS INC·Filed 2018·Granted Dec 3, 2019·10 cites·20 claims
- 0488US10742220B1Method and apparatus for operating programmable clock divider using reset pathsSYNOPSYS INC·Filed 2019·Granted Aug 11, 2020·7 cites·19 claims
- 0585US9467149B2Methods and systems for distributing clock and reset signals across an address macroKOOL CHIP INC·Filed 2014·Granted Oct 11, 2016·4 cites·14 claims
- 0684US9971975B2Optimal data eye for improved Vref marginINVECAS INC·Filed 2017·Granted May 15, 2018·7 cites·17 claims
- 0782US9564905B2Methods and systems for clocking a physical layer interfaceKOOL CHIP INC·Filed 2013·Granted Feb 7, 2017·4 cites·12 claims
- 0879US9715907B1Optimal data eye for improved Vref marginINVECAS INC·Filed 2016·Granted Jul 25, 2017·5 cites·10 claims
- 0979US9444463B2Voltage level shifterINVECAS INC·Filed 2015·Granted Sep 13, 2016·4 cites·9 claims
- 1078US10094859B1Voltage detectorINVECAS INC·Filed 2017·Granted Oct 9, 2018·2 cites·20 claims
- 1176US6222791B1Slew tolerant clock input buffer and a self-timed memory core thereofARTISAN COMPONENTS INC·Filed 2000·Granted Apr 24, 2001·24 cites·28 claims
- 1269US10014866B2Clock alignment scheme for data macros of DDR PHYINVECAS INC·Filed 2017·Granted Jul 3, 2018·2 cites·19 claims
- 1362US9286260B2Serial-to parallel converter using serially-connected stagesKOOL CHIP INC·Filed 2013·Granted Mar 15, 2016·1 cites·13 claims
- 1457US9337846B2Methods and systems for determining whether a receiver is present on a PCI-express busKOOL CHIP INC·Filed 2013·Granted May 10, 2016·0 cites·15 claims
- 1555US10502769B2Digital voltmeterINVECAS INC·Filed 2017·Granted Dec 10, 2019·0 cites·20 claims
- 1655US9948310B2Methods and systems for clocking a physical layer interfaceSOCTRONICS INC·Filed 2016·Granted Apr 17, 2018·0 cites·22 claims
- 1750US8952737B2Methods and systems for calibration of a delay locked loopKOOL CHIP INC·Filed 2013·Granted Feb 10, 2015·0 cites·19 claims
- 1847US2014312945A1Delay Locked LoopIPPILI SHARAT·Filed 2013·Application pending·0 cites
- 1943US9954538B2Clock alignment scheme for data macros of DDR PHYINVECAS INC·Filed 2016·Granted Apr 24, 2018·0 cites·7 claims
- 2043US9716492B1Method and circuit for duty cycle detectionINVECAS INC·Filed 2016·Granted Jul 25, 2017·0 cites·18 claims
- 2141US10361684B2Duty cycle detectionINVECAS INC·Filed 2017·Granted Jul 23, 2019·0 cites·10 claims
- 2239US10791203B2Multi-protocol receiverSYNOPSYS INC·Filed 2017·Granted Sep 29, 2020·0 cites·19 claims
- 2338US9349421B2Memory interfaceKOOL CHIP INC·Filed 2014·Granted May 24, 2016·0 cites·14 claims
- 2438US2013009669A1Voltage Mode DriverKOOL CHIP INC·Filed 2011·Application pending·0 cites
- 2537US8643516B1Parallel-to-serial converterRAO VENKATA N S N·Filed 2012·Granted Feb 4, 2014·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →