Inventor · disambiguated record
Vivek Chickermane
Also filed as: CHICKERMANE VIVEK
56 granted patents·467 citations·filing 2006–2023
98Inventor score
Files withCADENCE DESIGN SYSTEMS INC43THIRUNAVUKARASU SENTHIL ARASU6CHAKRAVADHANULA KRISHNA2WANG QI2CHAKRAVADHANULA KRISHNA V1
Top patents by PatentIndex Score
56 records- 0197US8904256B1Method and apparatus for low-pin count testing of integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Dec 2, 2014·35 cites·27 claims
- 0295US8650524B1Method and apparatus for low-pin count testing of integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Feb 11, 2014·41 cites·24 claims
- 0394US9702934B1Reducing mask data volume with elastic compressionCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jul 11, 2017·7 cites·20 claims
- 0494US7739629B2Method and mechanism for implementing electronic designs having power information specifications backgroundCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 15, 2010·42 cites·29 claims
- 0593US12055586B13D stacked die testing structureCADENCE DESIGN SYSTEMS INC·Filed 2023·Granted Aug 6, 2024·2 cites·20 claims
- 0693US11256839B1IP block scan chain constructionCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Feb 22, 2022·4 cites·20 claims
- 0793US9606179B1Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializerCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Mar 28, 2017·7 cites·18 claims
- 0893US7877715B1Method and apparatus to use physical design information to detect IR drop prone test patternsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Jan 25, 2011·18 cites·7 claims
- 0993US7693676B1Low power scan test for integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 6, 2010·24 cites·31 claims
- 1091US8468404B1Method and system for reducing switching activity during scan-load operationsCHICKERMANE VIVEK·Filed 2010·Granted Jun 18, 2013·28 cites·24 claims
- 1191US8429593B1Method and apparatus to use physical design information to detect IR drop prone test patternsTHIRUNAVUKARASU SENTHIL ARASU·Filed 2012·Granted Apr 23, 2013·7 cites·4 claims
- 1290US11379644B1IC chip test engineCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Jul 5, 2022·3 cites·20 claims
- 1390US9513335B1Method for using XOR trees for physically efficient scan compression and decompression logicCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 6, 2016·5 cites·10 claims
- 1490US9501590B1Systems and methods for testing integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 22, 2016·9 cites·11 claims
- 1590US9470756B1Method for using sequential decompression logic for VLSI test in a physically efficient constructionCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·5 cites·20 claims
- 1689US8516422B1Method and mechanism for implementing electronic designs having power information specifications backgroundWANG QI·Filed 2010·Granted Aug 20, 2013·13 cites·31 claims
- 1788US8595681B1Method and apparatus to use physical design information to detect IR drop prone test patternsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Nov 26, 2013·4 cites·6 claims
- 1888US8336019B1Method and apparatus to use physical design information to detect IR drop prone test patternsTHIRUNAVUKARASU SENTHIL ARASU·Filed 2011·Granted Dec 18, 2012·5 cites·14 claims
- 1988US7926012B1Design-For-testability plannerCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 12, 2011·26 cites·18 claims
- 2087US11947887B1Test-point flop sharing with improved testability in a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Apr 2, 2024·1 cites·20 claims
- 2187US9817068B1Method and system for improving efficiency of sequential test compression using overscanCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 14, 2017·4 cites·12 claims
- 2287US9465896B1Systems and methods for testing integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 11, 2016·6 cites·13 claims
- 2387US8732632B1Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect testCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 20, 2014·17 cites·14 claims
- 2487US8001433B1Scan testing architectures for power-shutoff aware systemsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Aug 16, 2011·15 cites·21 claims
- 2586US9470754B1Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serializationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·3 cites·20 claims
- 2685US10528689B1Verification process for IJTAG based test pattern migrationCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 7, 2020·7 cites·20 claims
- 2785US10417363B1Power and scan resource reduction in integrated circuit designs having shift registersCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 17, 2019·6 cites·14 claims
- 2885US10331506B1SoC top-level XOR compactor design to efficiently test and diagnose multiple identical coresCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jun 25, 2019·4 cites·17 claims
- 2985US8286123B1Method and apparatus to use physical design information to detect IR drop prone test patternsTHIRUNAVUKARASU SENTHIL ARASU·Filed 2011·Granted Oct 9, 2012·4 cites·16 claims
- 3085US7979764B2Distributed test compression for integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jul 12, 2011·16 cites·21 claims
- 3182US10955470B1Method to improve testability using 2-dimensional exclusive or (XOR) gridsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 23, 2021·2 cites·9 claims
- 3282US10775435B1Low-power shift with clock staggeringCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 15, 2020·3 cites·12 claims
- 3381US10740515B1Devices and methods for test point insertion coverageCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Aug 11, 2020·6 cites·20 claims
- 3481US7886263B1Testing to prescribe state capture by, and state retrieval from scan registersCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Feb 8, 2011·9 cites·19 claims
- 3581US7779381B2Test generation for low power circuitsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Aug 17, 2010·18 cites·19 claims
- 3680US9817069B1Method and system for construction of a highly efficient and predictable sequential test decompression logicCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 14, 2017·2 cites·20 claims
- 3780USRE44479EMethod and mechanism for implementing electronic designs having power information specifications backgroundWANG QI·Filed 2012·Granted Sep 3, 2013·5 cites·29 claims
- 3879US8438528B1Method and apparatus to use physical design information to detect IR drop prone test patternsTHIRUNAVUKARASU SENTHIL ARASU·Filed 2012·Granted May 7, 2013·2 cites·3 claims
- 3977US10761131B1Method for optimally connecting scan segments in two-dimensional compression chainsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 1, 2020·2 cites·20 claims
- 4077US9470755B1Method for dividing testable logic into a two-dimensional grid for physically efficient scanCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·2 cites·20 claims
- 4177US8392868B1Method and apparatus to use physical design information to detect IR drop prone test patternsTHIRUNAVUKARASU SENTHIL ARASU·Filed 2011·Granted Mar 5, 2013·2 cites·16 claims
- 4277US8296703B1Fault modeling for state retention logicCHAKRAVADHANULA KRISHNA·Filed 2008·Granted Oct 23, 2012·9 cites·26 claims
- 4375US8271226B2Testing state retention logic in low power systemsCHAKRAVADHANULA KRISHNA·Filed 2008·Granted Sep 18, 2012·8 cites·23 claims
- 4473US7944285B1Method and apparatus to detect manufacturing faults in power switchesCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted May 17, 2011·10 cites·10 claims
- 4572US8615692B1Method and system for analyzing test vectors to determine toggle countsKHURANA RAJESH·Filed 2009·Granted Dec 24, 2013·8 cites·30 claims
- 4671US10234504B1Optimizing core wrappers in an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Mar 19, 2019·2 cites·16 claims
- 4771US8584074B1Testing to prescribe state capture by, and state retrieval from scan registersTHIRUNAVUKARASU SENTHIL ARASU·Filed 2011·Granted Nov 12, 2013·2 cites·20 claims
- 4869US10796041B1Compacting test patterns for IJTAG testCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Oct 6, 2020·2 cites·20 claims
- 4967US8296694B1System and method for automated synthesis of circuit wrappersCHAKRAVADHANULA KRISHNA V·Filed 2009·Granted Oct 23, 2012·5 cites·33 claims
- 5061US12430474B1Locking mechanism and core wrapping for IP coreCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Sep 30, 2025·0 cites·20 claims
Showing the top 50 of 56 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →