Inventor · disambiguated record
Vikas Kohli
Also filed as: KOHLI VIKAS
22 granted patents·402 citations·filing 2002–2021
96Inventor score
Files withCADENCE DESIGN SYSTEMS INC13BHATTACHARYA UTPAL3KOHLI VIKAS2BANK OF NEW YORK MELLON1CADENCE DESIGN SYSTEMS1
Top patents by PatentIndex Score
22 records- 0197US9223915B1Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 29, 2015·39 cites·20 claims
- 0293US10285276B1Method and apparatus to drive layout of arbitrary EM-coil through parametrized cellCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted May 7, 2019·17 cites·19 claims
- 0393US9280621B1Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 8, 2016·12 cites·20 claims
- 0492US9361415B1Method, system, and computer program product for implementing a multi-fabric electronic design spanning across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jun 7, 2016·10 cites·20 claims
- 0592US9348960B1Method, system, and computer program product for probing or netlisting a multi-fabric electronic design spanning across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted May 24, 2016·10 cites·20 claims
- 0692US7143341B1Method and apparatus for concurrent engineering and design synchronization of multiple toolsCADENCE DESIGN SYSTEMS·Filed 2002·Granted Nov 28, 2006·95 cites·27 claims
- 0791US9619605B1System and method for automatically enforcing schematic layout strategy selectively applied to schematic objectsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Apr 11, 2017·17 cites·17 claims
- 0889US8438524B1Hierarchical editing of printed circuit board pin assignmentKOHLI VIKAS·Filed 2009·Granted May 7, 2013·26 cites·24 claims
- 0989US8316342B1Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layoutKUKAL TARANJIT·Filed 2010·Granted Nov 20, 2012·24 cites·28 claims
- 1089US7168041B1Method and apparatus for table and HDL based design entryCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jan 23, 2007·72 cites·14 claims
- 1187US9122384B1System and method for maintaining dynamic visual cue for associated circuitry of schematic objectCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Sep 1, 2015·10 cites·20 claims
- 1286US7990375B2Virtual view schematic editorCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Aug 2, 2011·20 cites·25 claims
- 1383US10289788B1System and method for suggesting components associated with an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted May 14, 2019·5 cites·15 claims
- 1478US8316337B2Method and system for optimally placing and assigning interfaces in a cross-fabric design environmentBHATTACHARYA UTPAL·Filed 2009·Granted Nov 20, 2012·10 cites·44 claims
- 1577US8527929B2Method and system for optimally connecting interfaces across multiple fabricsBHATTACHARYA UTPAL·Filed 2009·Granted Sep 3, 2013·9 cites·33 claims
- 1677US8479134B2Method and system for specifying system level constraints in a cross-fabric design environmentBHATTACHARYA UTPAL·Filed 2009·Granted Jul 2, 2013·9 cites·32 claims
- 1776US10606974B1System and method for dynamic visual guidance of mutually paired components in a circuit design editorCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 31, 2020·4 cites·12 claims
- 1874US8271933B1Pin unspecific device planning for printed circuit board layoutKOHLI VIKAS·Filed 2009·Granted Sep 18, 2012·11 cites·17 claims
- 1969US9202006B1System and method for connecting components in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 1, 2015·2 cites·20 claims
- 2057US11770499B2Aligning video conference participant windowsJPMORGAN CHASE BANK NA·Filed 2021·Granted Sep 26, 2023·0 cites·14 claims
- 2138US11593437B1System, method, and computer program product for implementing intelligent electronic design reuse through data analyticsCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Feb 28, 2023·0 cites·14 claims
- 2230US11887013B2System and method for facilitating model-based classification of transactionsBANK OF NEW YORK MELLON·Filed 2018·Granted Jan 30, 2024·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →