Inventor · disambiguated record
Viktor Markov
Also filed as: MARKOV VIKTOR
13 granted patents·3 pending applications·322 citations·filing 2007–2024
89Inventor score
Top patents by PatentIndex Score
16 records- 0197US7927994B1Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturingSILICON STORAGE TECH INC·Filed 2010·Granted Apr 19, 2011·73 cites·6 claims
- 0297US7868375B2Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturingSILICON STORAGE TECH INC·Filed 2009·Granted Jan 11, 2011·230 cites·2 claims
- 0387US11205490B2Method of improving read current stability in analog non-volatile memory cells by screening memory cellsSILICON STORAGE TECH INC·Filed 2020·Granted Dec 21, 2021·2 cites·20 claims
- 0480US10838652B2Programming of memory cell having gate capacitively coupled to floating gateSILICON STORAGE TECH INC·Filed 2018·Granted Nov 17, 2020·3 cites·32 claims
- 0580US8488388B2Method of programming a split gate non-volatile floating gate memory cell having a separate erase gateMARKOV VIKTOR·Filed 2011·Granted Jul 16, 2013·8 cites·7 claims
- 0674US11309042B2Method of improving read current stability in analog non-volatile memory by program adjustment for memory cells exhibiting random telegraph noiseSILICON STORAGE TECH INC·Filed 2020·Granted Apr 19, 2022·1 cites·18 claims
- 0766US10079061B2System and method for programming split-gate, non-volatile memory cellsSILICON STORAGE TECH INC·Filed 2016·Granted Sep 18, 2018·3 cites·8 claims
- 0865US10991433B2Method of improving read current stability in analog non-volatile memory by limiting time gap between erase and programSILICON STORAGE TECH INC·Filed 2020·Granted Apr 27, 2021·0 cites·12 claims
- 0964US11017866B2Method of improving read current stability in analog non-volatile memory using final bake in predetermined program stateSILICON STORAGE TECH INC·Filed 2020·Granted May 25, 2021·0 cites·5 claims
- 1059US2025234536A1Non-volatile memory cell with ono compound insulation layer between floating and control gates and a method of fabricationSILICON STORAGE TECH INC·Filed 2024·Application pending·0 cites
- 1157US12014793B2Method of screening non-volatile memory cellsSILICON STORAGE TECH INC·Filed 2022·Granted Jun 18, 2024·0 cites·9 claims
- 1251US11769558B2Method of reducing random telegraph noise in non-volatile memory by grouping and screening memory cellsSILICON STORAGE TECH INC·Filed 2021·Granted Sep 26, 2023·0 cites·10 claims
- 1351US8576648B2Method of testing data retention of a non-volatile memory cell having a floating gateMARKOV VIKTOR·Filed 2011·Granted Nov 5, 2013·2 cites·6 claims
- 1449US2009039410A1Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of ManufacturingLIU XIAN·Filed 2007·Application pending·0 cites
- 1547US2011127599A1Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of ManufacturingLIU XIAN·Filed 2011·Application pending·0 cites
- 1644US12080355B2Method of improving read current stability in analog non-volatile memory by post-program tuning for memory cells exhibiting random telegraph noiseSILICON STORAGE TECH INC·Filed 2021·Granted Sep 3, 2024·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →