Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing

Abstract

An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

1 . A non-volatile memory cell in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate; a select gate insulated and spaced apart from a first portion of the channel region; a floating gate insulated and spaced apart from a second portion of the channel region; the floating gate having a first end closest to the select gate and a second end furthest away from the select gate; an erase gate insulated and spaced apart from the substrate closest to the second end of the floating gate; a control gate insulated and spaced apart from the floating gate, the select gate and the erase gate and positioned above the floating gate and is between the erase gate and the select gate, wherein the improvement comprising:
 the erase gate having two electrically connected portions: a first portion laterally adjacent to and insulated from the second end of the floating gate and a second portion overlying and insulated from the floating gate and adjacent to the control gate;   wherein the second portion of the erase gate being separated from the floating gate by a first length measured in a direction substantially perpendicular to the direction from the first region to the second region;   wherein the second portion of the erase gate has an end closest to the control gate, and the first portion of the erase gate has an end closest to the floating gate;   wherein the second portion of the erase gate overlies the floating gate by a second length measured from the end of the second portion of the erase gate closest to the control gate to the end of the first portion of the erase gate closest to the floating gate in a direction substantially perpendicular to the first length direction; and   wherein the ratio of the second length to the first length is between approximately 1.0 and 2.5.   
   
   
       2 . The cell of  claim 1  wherein said two portions of the erase gate are monolithically formed. 
   
   
       3 . The cell of  claim 1  wherein said two portions of the erase gate are two separate portions electrically connected together. 
   
   
       4 . The cell of  claim 2  wherein said floating gate has a sharp corner, said corner being at the second end of the floating gate closest to the first portion of the erase gate. 
   
   
       5 . The cell of  claim 4  wherein the corner facilitates electron flow from the floating gate to the erase gate during the erase operation. 
   
   
       6 . The cell of  claim 2  wherein said floating gate is insulated and spaced apart from a portion of the second region and said erase gate is insulated and spaced apart from the second region. 
   
   
       7 . The cell of  claim 6  wherein the first portion of the channel region over which the select gate is insulated and spaced apart from abuts the first region. 
   
   
       8 . The cell of  claim 2  wherein said select gate is separated from the first end of the floating gate by a composite insulating material. 
   
   
       9 . The cell of  claim 8  wherein the composite insulating material is silicon dioxide and silicon nitride. 
   
   
       10 . The cell of  claim 2  wherein said select gate is separated from the first end of the floating gate by a homogeneous insulating material. 
   
   
       11 . The cell of  claim 10  wherein said homogeneous insulating material is silicon dioxide. 
   
   
       12 . An array of non-volatile memory cells comprising:
 a substrate of a substantially single crystalline material of a first conductivity type;   a plurality of non-volatile memory cells arranged in a plurality of rows and columns, with each cell having:   a first region of a second conductivity type in the substrate;   a second region of the second conductivity type in the substrate;   a channel region between the first region and the second region in the substrate;   a select gate insulated and spaced apart from a first portion of the channel region;   a floating gate insulated and spaced apart from a second portion of the channel region, the floating gate having a first end closest to the select gate and a second end furthest away from the select gate;   an erase gate insulated and spaced apart from the substrate closest to the second end of the floating gate;   a control gate insulated and spaced apart from the floating gate, the select gate and the erase gate and positioned above the floating gate and is between the erase gate and the select gate;   wherein the erase gate has two electrically connected portions: a first portion laterally adjacent to and insulated from the second end of the floating gate and a second portion overlying and insulated from the floating gate and adjacent to the control gate;   wherein the second portion of the erase gate being separated from the floating gate by a first length measured in a direction substantially perpendicular to the direction from the first region to the second region;   wherein the second portion of the erase gate has an end closest to the control gate, and the first portion of the erase gate has an end closest to the floating gate, wherein the second portion of the erase gate overlies the floating gate by a second length measured from the end of the second portion of the erase gate to the end of the first portion of the erase gate in a direction substantially perpendicular to the first length direction;   wherein the ratio of the second length to the first length is between approximately 1.0 and 2.5;   wherein cells adjacent to one another on one side have a common first region and cells adjacent to one another on another side have a common second region.   
   
   
       13 . The array of  claim 12  wherein cells adjacent to one another on another side have a common erase gate. 
   
   
       14 . The array of  claim 13  wherein said two portions of the erase gate are monolithically formed. 
   
   
       15 . The array of  claim 12  wherein said two portions of the erase gate are two separate portions electrically connected together. 
   
   
       16 . The array of  claim 14  wherein said floating gate has a sharp corner, said corner being at the second end of the floating gate closest to the first portion of the erase gate. 
   
   
       17 . The array of  claim 16  wherein the corner is for facilitating electron flow from the floating gate to the erase gate during the erase operation. 
   
   
       18 . The array of  claim 14  wherein said floating gate is insulated and spaced apart from a portion of the second region and said erase gate is insulated and spaced apart from the second region. 
   
   
       19 . The array of  claim 18  wherein the first portion of the channel region over which the select gate is insulated and spaced apart from abuts the first region. 
   
   
       20 . The array of  claim 12  wherein said select gate is separated from the first end of the floating gate by a composite insulating material. 
   
   
       21 . The array of  claim 20  wherein said composite insulating material is silicon dioxide and silicon nitride. 
   
   
       22 . The array of  claim 12  wherein said select gate is separated from the first end of the floating gate by a homogeneous insulating material. 
   
   
       23 . The array of  claim 22  wherein said homogeneous insulating material is silicon dioxide.