Inventor · disambiguated record
Viswanathan Nagarajan
Also filed as: NAGARAJAN VISWANATHAN
17 granted patents·1 pending application·79 citations·filing 2009–2024
92Inventor score
Top patents by PatentIndex Score
18 records- 0193US7961123B2Time-interleaved analog-to-digital converterTEXAS INSTRUMENTS INC·Filed 2009·Granted Jun 14, 2011·31 cites·18 claims
- 0292US10103753B1Error correcting analog-to-digital convertersTEXAS INSTRUMENTS INC·Filed 2017·Granted Oct 16, 2018·12 cites·20 claims
- 0389US11955984B2Analog-to-digital converter (ADC) having selective comparator offset error tracking and related correctionsTEXAS INSTRUMENTS INC·Filed 2022·Granted Apr 9, 2024·4 cites·20 claims
- 0488US11962318B2Calibration scheme for a non-linear ADCTEXAS INSTRUMENTS INC·Filed 2022·Granted Apr 16, 2024·2 cites·20 claims
- 0587US12074607B2Analog-to-digital converter (ADC) having linearization circuit with reconfigurable lookup table (LUT) memory and calibration optionsTEXAS INSTRUMENTS INC·Filed 2022·Granted Aug 27, 2024·2 cites·21 claims
- 0684US9748966B2Histogram based error estimation and correctionTEXAS INSTRUMENTS INC·Filed 2016·Granted Aug 29, 2017·7 cites·20 claims
- 0778US7898446B2Correction of sampling mismatch in time-interleaved analog-to-digital convertersTEXAS INSTRUMENTS INC·Filed 2009·Granted Mar 1, 2011·11 cites·16 claims
- 0874US10581406B2Digital filtering for analog gain/phase errorsTEXAS INSTRUMENTS INC·Filed 2018·Granted Mar 3, 2020·4 cites·20 claims
- 0972US12512846B2Analog-to-digital converter (ADC) having linearization circuit with reconfigurable lookup table (LUT) memory and calibration optionsTEXAS INSTRUMENTS INC·Filed 2024·Granted Dec 30, 2025·0 cites·20 claims
- 1071US12494794B2Analog-to-digital converter (ADC) having selective comparator offset error tracking and related correctionsTEXAS INSTRUMENTS INC·Filed 2024·Granted Dec 9, 2025·0 cites·21 claims
- 1169US10320405B2Pattern based estimation of errors in ADCTEXAS INSTRUMENTS INC·Filed 2018·Granted Jun 11, 2019·2 cites·26 claims
- 1265US10541700B2Gain and memory error estimation in a pipeline analog to digital converterTEXAS INSTRUMENTS INC·Filed 2019·Granted Jan 21, 2020·1 cites·20 claims
- 1359US9941893B2Pattern based estimation of errors in ADCTEXAS INSTRUMENTS INC·Filed 2017·Granted Apr 10, 2018·1 cites·25 claims
- 1454US11881867B2Calibration scheme for filling lookup table in an ADCTEXAS INSTRUMENTS INC·Filed 2021·Granted Jan 23, 2024·0 cites·22 claims
- 1554US11309902B2Gain and memory error estimation in a pipeline analog to digital converterTEXAS INSTRUMENTS INC·Filed 2019·Granted Apr 19, 2022·0 cites·20 claims
- 1652US8390488B2Non-linearity correction that is independent of input common mode, temperature variation, and process variationKIRAN GANESH·Filed 2011·Granted Mar 5, 2013·2 cites·15 claims
- 1751US2025373237A1Methods and apparatus to drive inductor-capacitor (lc) circuitry with subharmonic injectionTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 1850US10419036B2Error correcting analog-to-digital convertersTEXAS INSTRUMENTS INC·Filed 2018·Granted Sep 17, 2019·0 cites·11 claims
Join the waitlist — get patent alerts
Get an alert when Viswanathan Nagarajan files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →