US7961123B2ActiveUtilityA1
Time-interleaved analog-to-digital converter
Est. expiryJul 9, 2029(~3 yrs left)· nominal 20-yr term from priority
Inventors:Viswanathan NagarajanSriram MuraliSthanunathan RamakrishnanVisvesvaraya PentakotaJaiganesh Balakrishnan
H03M 1/0836H03M 1/1057H03M 1/1215
93
PatentIndex Score
31
Cited by
22
References
18
Claims
Abstract
A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least one of the clock signals so as to sample an input signal that is generally wide-sense stationary at sampling instants, where correlation function exist between samples from a two or more of the ADCs that is a function of the time differences between associated sampling instants. The estimator is coupled to each of the adjustable delay elements and each of the ADCs so as to calculate the correlation function and adjust the adjustable delay elements to account for sampling mismatch between the ADCs based at least in part on the correlation function.
Claims
exact text as granted — not AI-modified1. An apparatus comprising:
a clock generator that generates a plurality of clock signals;
a plurality of analog-to-digital converters (ADCs), wherein each ADC is associated with at least one of the clock signals so as to sample an input signal at a plurality of sampling instants, and wherein a correlation function exists between samples from a two or more of the ADCs;
a correction circuit that is coupled between the clock generator and at least one of the ADCs; and
an estimator that is coupled to the correction circuit and each of the ADCs, wherein the estimator calculates the correlation function and iteratively provides adjustments to the correction circuit to account for sampling mismatch between the plurality of ADCs by employing a gradient descent formulation for a predetermined cost function, wherein the predetermined cost function is a function of the correlation function.
2. The apparatus of claim 1 , wherein the correlation function that is a function of the time differences between associated sampling instants.
3. The apparatus of claim 1 , wherein the correction circuit further comprises a plurality of adjustable delay elements, wherein each adjustable delay element is coupled between the clock generator and at least one of the ADCs, and wherein the estimator adjusts at least one of the adjustable delay elements to account for sampling mismatch between the plurality of ADCs based at least in part on the correlation function.
4. The apparatus of claim 1 , wherein the clock generator further comprises a divider.
5. The apparatus of claim 1 , wherein the predetermined cost function (V) is:
V
=
∑
i
=
1
M
(
R
i
-
1
,
i
-
R
xx
(
T
s
)
R
xx
′
(
T
s
)
)
2
=
∑
i
=
1
M
(
R
xx
(
T
s
+
δ
i
-
δ
i
-
1
)
-
R
xx
(
T
s
)
R
xx
′
(
T
s
)
)
2
,
so that
Δ i n+1 =Δ i n +μ( R i−1,i −R i,i+1 )
wherein R lm denotes the correlation function between the l th and m th ADCs, Δ j k denotes a delay for the k th iteration of the j th delay element, δ p is a timing error for the p th ADC, and μ is less than 1 and greater than 0.
6. The apparatus of claim 1 , wherein the predetermined cost function (V) is:
V
=
∑
i
=
1
M
(
R
i
-
1
,
i
-
R
xx
(
T
s
)
R
xx
′
(
T
s
)
)
2
=
∑
i
=
1
M
(
R
xx
(
T
s
+
δ
i
-
δ
i
-
1
)
-
R
xx
(
T
s
)
R
xx
′
(
T
s
)
)
2
,
so that
Δ
i
n
+
1
=
Δ
i
n
-
μ
(
2
(
R
i
-
1
,
i
-
R
i
,
i
+
1
)
R
xx
′
(
T
s
)
)
,
wherein R lm denotes the correlation function between the l th and m th ADCs, Δ j k denotes a delay for the k th iteration of the jth delay element, δ p is a delay for the p th ADC, and μ is less than 1 and greater than 0.
7. An apparatus comprising:
a clock generator that generates a plurality of clock signals;
a plurality of analog-to-digital converters (ADCs), wherein each ADC is associated with at least one of the clock signals so as to sample an input signal at a plurality of sampling instants, and wherein a correlation function exists between samples from a two or more of the ADCs;
a correction circuit that is coupled between the clock generator and at least one of the ADCs;
an estimator that is coupled to the correction circuit and each of the ADCs, wherein the estimator calculates the correlation function and provides an adjustment to the correction circuit to account for sampling mismatch between the plurality of ADCs based at least in part on the correlation function;
a differentiator that receives the input signal; and
a coarse ADC that is coupled to the differentiator, the estimator, and the clock generator, wherein at least one of the clock signals is associated with the coarse ADC.
8. The apparatus of claim 1 , wherein at least one of the plurality of ADCs is a coarse ADC.
9. The apparatus of claim 8 , wherein the cost function is a function of differences between associated sampling instants from the coarse ADC and at least one of the other ADCs.
10. An apparatus comprising:
a clock generator that generates a plurality of clock signals;
a plurality of analog-to-digital converters (ADCs), wherein each ADC is associated with at least one of the clock signals so as to sample an input signal at a plurality of sampling instants, and wherein a correlation function exists between samples from a two or more of the ADCs;
a correction circuit that is coupled between the clock generator and at least one of the ADCs; and
an estimator that is coupled to the correction circuit and each of the ADCs, wherein the estimator has a computer program product embodied thereon that includes:
computer code for calculating the correlation function; and
computer code for iteratively providing adjustments to the correction circuit to account for sampling mismatch between the plurality of ADCs by employing a gradient descent formulation for a predetermined cost function, wherein the predetermined cost function is a function of the correlation function.
11. The apparatus of claim 10 , wherein the correlation function that is a function of the time differences between associated sampling instants.
12. The apparatus of claim 10 , wherein the correction circuit further comprises a plurality of adjustable delay elements, wherein each adjustable delay element is coupled between the clock generator and at least one of the ADCs, and wherein the estimator adjusts at least one of the adjustable delay elements to account for sampling mismatch between the plurality of ADCs based at least in part on the correlation function.
13. The apparatus of claim 10 , wherein the clock generator further comprises a divider.
14. The apparatus of claim 10 , wherein the predetermined cost function (V) is:
V
=
∑
i
=
1
M
(
R
i
-
1
,
i
-
R
xx
(
T
s
)
R
xx
′
(
T
s
)
)
2
=
∑
i
=
1
M
(
R
xx
(
T
s
+
δ
i
-
δ
i
-
1
)
-
R
xx
(
T
s
)
R
xx
′
(
T
s
)
)
2
,
so that
Δ i n+1 =Δ i n +μ( R i−1,i −R i,i+1 ),
wherein R lm denotes the correlation function between the l th and m th ADCs, Δ j k denotes a delay for the k th iteration of the j th delay element, δ p is a timing error for the p th ADC, and μ is less than 1 and greater than 0.
15. The apparatus of claim 10 , wherein the predetermined cost function (V) is:
V
=
∑
i
=
1
M
(
R
i
-
1
,
i
-
R
xx
(
T
s
)
R
xx
′
(
T
s
)
)
2
=
∑
i
=
1
M
(
R
xx
(
T
s
+
δ
i
-
δ
i
-
1
)
-
R
xx
(
T
s
)
R
xx
′
(
T
s
)
)
2
,
so that
Δ
i
n
+
1
=
Δ
i
n
-
μ
(
2
(
R
i
-
1
,
i
-
R
i
,
i
+
1
)
R
xx
′
(
T
s
)
)
,
wherein R lm denotes the correlation function between the l th and m th ADCs, Δ j k denotes a delay for the k th iteration of the jth delay element, δ p is a delay for the p th ADC, and μ is less than 1 and greater than 0.
16. An apparatus comprising:
a clock generator that generates a plurality of clock signals;
a plurality of analog-to-digital converters (ADCs), wherein each ADC is associated with at least one of the clock signals so as to sample an input signal at a plurality of sampling instants, and wherein a correlation function exists between samples from a two or more of the ADCs;
a correction circuit that is coupled between the clock generator and at least one of the ADCs;
an estimator that is coupled to the correction circuit and each of the ADCs, wherein the estimator has a computer program product embodied thereon that includes:
computer code for calculating the correlation function; and
computer code for providing adjustments to the correction circuit to account for sampling mismatch between the plurality of ADCs based at least in part on the correlation function;
a differentiator that receives the input signal; and
a coarse ADC that is coupled to the differentiator, the estimator, and the clock generator, wherein at least one of the clock signals is associated with the coarse ADC.
17. The apparatus of claim 10 , wherein the apparatus further comprises at least one of the plurality of ADCs is a coarse ADC.
18. The apparatus of claim 17 , wherein the correlation function is a function of differences between associated sampling instants from the coarse ADC and at least one of the other ADCs.Cited by (0)
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