Inventor · disambiguated record
Vinaya Kumar Singh
Also filed as: SINGH VINAYA K · SINGH VINAYA KUMAR
9 granted patents·72 citations·filing 2004–2010
88Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0187US7810056B1Method and system for implementing context aware synthesis of assertionsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Oct 5, 2010·25 cites·24 claims
- 0276US7984401B2Method for checking a status of a signal port to identify an over-constrained eventCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Jul 19, 2011·6 cites·12 claims
- 0375US8104001B2Automated debugging method for over-constrained circuit verification environmentLEHAVOT AMIR·Filed 2008·Granted Jan 24, 2012·6 cites·12 claims
- 0473US8099695B1Automated debugging method and system for over-constrained circuit verification environmentLEHAVOT AMIR·Filed 2006·Granted Jan 17, 2012·5 cites·14 claims
- 0570US8099696B2Method for providing information associated with an over-constrained event in verification of a circuit designLEHAVOT AMIR·Filed 2008·Granted Jan 17, 2012·4 cites·9 claims
- 0669US7712060B1Method and system for handling assertion libraries in functional verificationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 4, 2010·7 cites·34 claims
- 0769US7428712B1Design optimization using approximate reachability analysisCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Sep 23, 2008·5 cites·17 claims
- 0865US7386813B2Transformation of simple subset of PSL into SERE implication formulas for verification with model checking and simulation engines using semantic preserving rewrite rulesCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Jun 10, 2008·12 cites·53 claims
- 0959US8671395B1Adaptive deadend avoidance in constrained simulationYUAN JUN·Filed 2010·Granted Mar 11, 2014·2 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →