Inventor · disambiguated record
Victor Torres
Also filed as: TORRES VICTOR · TORRES VICTOR M · TORRES VICTOR MARIO
20 granted patents·4 pending applications·150 citations·filing 1999–2023
94Inventor score
Top patents by PatentIndex Score
24 records- 0194US7410879B1System and method for providing a dual via architecture for thin film resistorsNAT SEMICONDUCTOR CORP·Filed 2005·Granted Aug 12, 2008·34 cites·20 claims
- 0290US10002760B2Method for manufacturing SiC wafer fit for integration with power device manufacturing technologyDOW CORNING·Filed 2016·Granted Jun 19, 2018·8 cites·24 claims
- 0389US7332403B1System and method for providing a buried thin film resistor having end caps defined by a dielectric maskNAT SEMICONDUCTOR CORP·Filed 2005·Granted Feb 19, 2008·17 cites·20 claims
- 0486US9279192B2Method for manufacturing SiC wafer fit for integration with power device manufacturing technologyDOW CORNING·Filed 2014·Granted Mar 8, 2016·8 cites·24 claims
- 0583US10014388B1Transient voltage suppression devices with symmetric breakdown characteristicsGEN ELECTRIC·Filed 2017·Granted Jul 3, 2018·4 cites·14 claims
- 0677US7585775B1System and method for faceting a masking layer in a plasma etch to slope a feature edgeNAT SEMICONDUCTOR CORP·Filed 2005·Granted Sep 8, 2009·6 cites·20 claims
- 0776US11764257B2Systems and methods for junction termination of wide band gap super-junction power devicesGEN ELECTRIC·Filed 2022·Granted Sep 19, 2023·0 cites·20 claims
- 0873US7808048B1System and method for providing a buried thin film resistor having end caps defined by a dielectric maskNAT SEMICONDUCTOR CORP·Filed 2007·Granted Oct 5, 2010·5 cites·20 claims
- 0972US7115500B1System and method for providing a dry-wet-dry etch procedure to create a sidewall profile of a viaNAT SEMICONDUCTOR CORP·Filed 2004·Granted Oct 3, 2006·15 cites·20 claims
- 1071US8765091B2Method to manufacture large uniform ingots of silicon carbide by sublimation/condensation processesLOBODA MARK·Filed 2008·Granted Jul 1, 2014·3 cites·12 claims
- 1170US2023167582A1SiC P-TYPE, AND LOW RESISTIVITY, CRYSTALS, BOULES, WAFERS AND DEVICES, AND METHODS OF MAKING THE SAMEPALLIDUS INC·Filed 2022·Application pending·0 cites
- 1270US2023167583A1SiC P-TYPE, AND LOW RESISTIVITY, CRYSTALS, BOULES, WAFERS AND DEVICES, AND METHODS OF MAKING THE SAMEPALLIDUS INC·Filed 2022·Application pending·0 cites
- 1370US2023167580A1SiC P-TYPE, AND LOW RESISTIVITY, CRYSTALS, BOULES, WAFERS AND DEVICES, AND METHODS OF MAKING THE SAMEPALLIDUS INC·Filed 2022·Application pending·0 cites
- 1469US7456097B1System and method for faceting via top corners to improve metal fillNAT SEMICONDUCTOR CORP·Filed 2004·Granted Nov 25, 2008·15 cites·20 claims
- 1566US6306675B1Method for forming a low-defect epitaxial layer in the fabrication of semiconductor devicesUNIV ARIZONA·Filed 1999·Granted Oct 23, 2001·32 cites·12 claims
- 1665US11271076B2Systems and methods for junction termination in semiconductor devicesGEN ELECTRIC·Filed 2019·Granted Mar 8, 2022·0 cites·20 claims
- 1765US11245003B2Systems and methods for junction termination of wide band gap super-junction power devicesGEN ELECTRIC·Filed 2019·Granted Feb 8, 2022·0 cites·21 claims
- 1855US2024071743A1ELECTROCHEMICAL SYSTEMS AND METHODS FOR FINISHING SiC WAFERSPALLIDUS INC·Filed 2023·Application pending·0 cites
- 1953US11986588B2Electronic systemPRESSPART GMBH & CO KG·Filed 2020·Granted May 21, 2024·0 cites·17 claims
- 2051US10969409B2Miniaturized current sensorsGEN ELECTRIC·Filed 2018·Granted Apr 6, 2021·0 cites·14 claims
- 2151US7960240B1System and method for providing a dual via architecture for thin film resistorsNAT SEMICONDUCTOR CORP·Filed 2008·Granted Jun 14, 2011·0 cites·20 claims
- 2251US7172973B1System and method for selectively modifying a wet etch rate in a large areaNAT SEMICONDUCTOR CORP·Filed 2004·Granted Feb 6, 2007·3 cites·21 claims
- 2350US10741551B2Integrated vertical and lateral semiconductor devicesGEN ELECTRIC·Filed 2018·Granted Aug 11, 2020·0 cites·20 claims
- 2440US10354871B2Sputtering system and method for forming a metal layer on a semiconductor deviceGEN ELECTRIC·Filed 2017·Granted Jul 16, 2019·0 cites·12 claims
Join the waitlist — get patent alerts
Get an alert when Victor Torres files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →