System and method for selectively modifying a wet etch rate in a large area

Abstract

A system and method is disclosed for selectively increasing a wet etch rate of a large raised area portion of a semiconductor wafer with respect to a wet etch rate of a small raised area portion of the semiconductor wafer. A resist mask on the semiconductor wafer is etched to create a large via over the large raised area portion and a small via over the small raised area portion. An ion implantation beam is applied with an impact direction that enables ions to pass through the large via but does not enable ions to pass through the small via. The ions that pass through the large via increase the wet etch rate of the underlying portion of the semiconductor wafer. In one embodiment the impact direction has a tilt angle of forty five degrees and a rotation angle of forty five degrees.

1. A method for selectively increasing a wet etch rate of a large raised area portion of a semiconductor wafer with respect to a wet etch rate of a small raised area portion of the semiconductor wafer, said method comprising the steps of:
 applying a resist mask layer to said semiconductor wafer; 
 etching said resist mask layer to create a large via over said large raised area portion of said semiconductor wafer; 
 etching said resist mask layer to create a small via over said small raised area portion of said semiconductor wafer; and 
 exposing said semiconductor wafer to ions of an ion implantation beam that has an implant direction that enables ions to pass through said large via but does not enable ions to pass through said small via. 
 
   
   
     2. The method as set forth in  claim 1  wherein said implant direction of said ion implantation beam is tilted at an acute angle with respect to a line that is perpendicular to the plane of the semiconductor wafer. 
   
   
     3. The method as set forth in  claim 2  wherein said acute angle of tilt is an angle of forty five degrees. 
   
   
     4. The method as set forth in  claim 2  wherein said implant direction of said ion implantation beam is rotated at an acute angle in the semiconductor wafer plane. 
   
   
     5. The method as set forth in  claim 4  wherein said acute angle of rotation is an angle of forty five degrees. 
   
   
     6. The method as set forth in  claim 4  wherein said large raised area portion of said semiconductor wafer comprises an alignment mark area and said large via comprises an align mark via. 
   
   
     7. The method as set forth in  claim 6  wherein said small raised area portion of said semiconductor wafer comprises an active device area and said small via comprises one of: a single via and a slot via. 
   
   
     8. The method as set forth in  claim 7  wherein said implant direction of said ion implantation beam is tilted at an acute angle with respect to a line that is perpendicular to the plane of the semiconductor wafer and rotated at an acute angle in the semiconductor wafer plane so that ions pass through said align mark via but do not pass through one of: said single via and said slot via. 
   
   
     9. The method as set forth in  claim 8  wherein said angle of tilt is an angle of forty five degrees and said angle of rotation is an angle of forty five degrees. 
   
   
     10. The method as set forth in  claim 8  further comprising the step of:
 applying a wet etch process to said large raised area portion of said semiconductor wafer that has been exposed to said ion implantation process and to said small raised area portion of said semiconductor wafer that has not been exposed to said ion implantation process. 
 
   
   
     11. The method as set forth in  claim 7  wherein said implant direction of said ion implantation beam is tilted at an acute angle with respect to a line that is perpendicular to the plane of the semiconductor wafer; and
 wherein said align mark via and said one of said single via and said slot via are disposed at an acute angle in the semiconductor wafer plane with respect to said implant direction of said ion implantation beam so that ions pass through said align mark via but do not pass through one of said single via and said slot via. 
 
   
   
     12. The method as set forth in  claim 11  wherein said angle of tilt is an angle of forty five degrees and said angle at which said align mark via and said one of said single via and said slot via are disposed is an angle of forty five degrees. 
   
   
     13. The method as set forth in  claim 1  wherein said large raised area portion of said semiconductor wafer comprises an alignment mark area and said large via comprises an align mark via. 
   
   
     14. The method as set forth in  claim 13  wherein said small raised area portion of said semiconductor wafer comprises an active device area and said small via comprises a single via. 
   
   
     15. The method as set forth in  claim 14  wherein said implant direction of said ion implantation beam is tilted at an acute angle with respect to a line that is perpendicular to the plane of the semiconductor wafer so that ions pass through said align mark via but do not pass through said single via. 
   
   
     16. The method as set forth in  claim 15  wherein said acute angle of tilt is an angle of forty five degrees. 
   
   
     17. The method as set forth in  claim 15  further comprising the step of:
 applying a wet etch process to said large raised area portion of said semiconductor wafer that has been exposed to said ion implantation process and to said small raised area portion of said semiconductor wafer that has not been exposed to said ion implantation process. 
 
   
   
     18. A method for selectively increasing a wet etch rate of an alignment mark area of a semiconductor wafer with respect to a wet etch rate of an active device portion of the semiconductor wafer, said method comprising the steps of:
 applying a resist mask layer to said semiconductor wafer; 
 etching said resist mask layer to create an align mark via over said alignment mark area of said semiconductor wafer; 
 etching said resist mask layer to create one of a single via and a slot via over said active device portion of said semiconductor wafer; and 
 exposing said semiconductor wafer to ions of an ion implantation beam that has an implant direction that enables ions to pass through said align mark via but does not enable ions to pass through said one of said single via and said slot via. 
 
   
   
     19. The method as set forth in  claim 18  wherein said implant direction of said ion implantation beam is tilted at an acute angle with respect to a line that is perpendicular to the plane of the semiconductor wafer and rotated at an acute angle in the semiconductor wafer plane so that ions pass through said align mark via but do not pass through one of said single via and said slot via. 
   
   
     20. The method as set forth in  claim 19  wherein said angle of tilt is an angle of forty five degrees and said angle of rotation is an angle of forty five degrees. 
   
   
     21. The method as set forth in  claim 19  further comprising the step of:
 applying a wet etch process to said alignment mark area of said semiconductor wafer that has been exposed to said ion implantation process and to said active device portion of said semiconductor wafer that has not been exposed to said ion implantation process.