Inventor · disambiguated record
Wan-Tung Liang
Also filed as: LIANG WAN-TUNG
3 granted patents·2 pending applications·0 citations·filing 2014–2019
39Inventor score
Files withEOREX CORP5
Top patents by PatentIndex Score
5 records- 0147US10638610B1Memory layout for absorbing and reducing reflection signalsEOREX CORP·Filed 2019·Granted Apr 28, 2020·0 cites·9 claims
- 0240US11048439B2Device of memory modulesEOREX CORP·Filed 2019·Granted Jun 29, 2021·0 cites·2 claims
- 0338US2015214172A1Memory and layout method of memory ball padsEOREX CORP·Filed 2014·Application pending·0 cites
- 0431US2015213841A1Memory chip and memory storage deviceEOREX CORP·Filed 2014·Application pending·0 cites
- 0530US10347302B1Memory layout for preventing reference layer from breaksEOREX CORP·Filed 2018·Granted Jul 9, 2019·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →