Memory layout for preventing reference layer from breaks

Abstract

A memory comprising substrates is provided. Each substrate comprises a through-hole area at center; a first contact area at a side of the through-hole area; and a second contact area at another side of the through-hole area. The substrate uses its first or second contact area to mutually electrically connects to the first or second contact area of the another substrate through the through-hole area. After the pins of the memory having at least PAR pin included are electrically connects to the first and second contact areas of the substrate, all the substrates obtain mutual connections across layers through signal lines with the guidance of the through-hole areas. Thus, on fabricating the memory, reference layer is effectively prevented from breaks with good power distribution and sufficient wiring space achieved while good signal integrity is further maintained.

What is claimed is: 
     
       1. A memory device assembly having a layout preventing a reference layer from breaks and comprising a memory device and a plurality of substrates, each one of said substrates comprising:
 a through-hole area, wherein said through-hole area is located at a center of one of said substrates to obtain connection; 
 a first contact area, wherein said first contact area is located at a side of said through-hole area on said one of said substrates to obtain connection and wherein said first contact area connects to pins of the memory device through signal lines; and 
 a second contact area, wherein said second contact area is located at another side of said through-hole area on said one of said substrates to obtain connection and wherein said second contact area connects to pins of the memory device through signal lines, wherein at least a command/address parity (PAR) pin is included in said pins of the memory device and wherein one of said substrates uses a corresponding contact area of said one of said substrates to be mutually electrically connected with another corresponding contact area of another one of said substrates and said corresponding contact area is selected from a group consisting of a corresponding first contact area and a corresponding second contact area. 
 
     
     
       2. The memory device assembly according to  claim 1 , wherein said through-hole area comprises a first through-hole row, a second through-hole row, and a third through-hole row and wherein said second through-hole row is located at a side of said first through-hole row in one direction and said third through-hole row is located at a side of said second through-hole row in said direction. 
     
     
       3. The memory device assembly according to  claim 2 , wherein said first through-hole row comprises eight instances of first through-hole; said second through-hole row comprises eight instances of second through-hole; and said third through-hole row comprises eight instances of third through-hole. 
     
     
       4. The memory device assembly according to  claim 3 , wherein a separating zone is deposed between every two neighboring rows in said first through-hole row, said second through-hole row, and said third through-hole row. 
     
     
       5. The memory device assembly according to  claim 3 , wherein each one of said first, said second, and said third through-holes has an insulating zone surrounding an outside edge. 
     
     
       6. The memory device assembly according to  claim 1 , wherein said first contact area comprises a first contact row, a second contact row and a third contact row said second contact row is located at a side of said first contact row in one direction and said third contact row is located at a side of said second contact row in said direction and wherein each one of said first contact row, said second contact row, and said third contact row comprises nine instances of first contact, second contact, and third contact, respectively. 
     
     
       7. The memory device assembly according to  claim 1 , wherein said second contact area comprises a fourth contact row, a fifth contact row, and a sixth contact row and wherein said fifth contact row is located at a side of said fourth contact row in one direction and said sixth contact row is located at a side of said fifth contact row in said direction and wherein each one of said first contact row, said second contact row, and said third contact row comprises nine instances of fourth contact, fifth contact, and sixth contact, respectively. 
     
     
       8. The memory device assembly according to  claim 1 , wherein each one of said first and said second contact areas of said one of said substrates uses corresponding signal lines to pass through two surfaces of said one of said substrates with said through-hole area of said one of said substrates to obtain an electrical connection to a contact area selected from a group consisting of said first contact area of another one of said substrates and said second contact area of another one of said substrates. 
     
     
       9. The memory device assembly according to  claim 8 , wherein said signal lines are of the same length.