Inventor · disambiguated record
Wei-Lun Kane Jen
Also filed as: JEN WEI · JEN WEI-LUN · JEN WEI-LUN K · JEN WEI-LUN KANE
34 granted patents·16 pending applications·96 citations·filing 2006–2025
96Inventor score
Top patents by PatentIndex Score
50 records- 0197US11521931B2Microelectronic structures including bridgesINTEL CORP·Filed 2020·Granted Dec 6, 2022·7 cites·18 claims
- 0296US11664290B2Package with underfill containment barrierINTEL CORP·Filed 2021·Granted May 30, 2023·3 cites·20 claims
- 0395US9548264B2High density organic bridge device and methodINTEL CORP·Filed 2016·Granted Jan 17, 2017·10 cites·20 claims
- 0494US12014989B2Device and method of very high density routing used with embedded multi-die interconnect bridgeINTEL CORP·Filed 2022·Granted Jun 18, 2024·1 cites·20 claims
- 0593US9704735B2Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabricationKONCHADY MANOHAR S·Filed 2014·Granted Jul 11, 2017·21 cites·25 claims
- 0691US9236366B2High density organic bridge device and methodINTEL CORP·Filed 2012·Granted Jan 12, 2016·14 cites·18 claims
- 0790US10624213B1Asymmetric electronic substrate and method of manufactureINTEL CORP·Filed 2018·Granted Apr 14, 2020·5 cites·8 claims
- 0890US10020262B2High resolution solder resist material for silicon bridge applicationINTEL CORP·Filed 2016·Granted Jul 10, 2018·7 cites·18 claims
- 0989US11158558B2Package with underfill containment barrierINTEL CORP·Filed 2016·Granted Oct 26, 2021·5 cites·16 claims
- 1089US2025323167A1Device and method of very high density routing used with embedded multi-die interconnect bridgeINTEL CORP·Filed 2025·Application pending·0 cites
- 1187US10629469B2Solder resist layers for coreless packages and methods of fabricationINTEL CORP·Filed 2017·Granted Apr 21, 2020·4 cites·4 claims
- 1286US2024321762A1High density organic bridge device and methodINTEL CORP·Filed 2024·Application pending·0 cites
- 1384US12327773B2Package with underfill containment barrierINTEL CORP·Filed 2024·Granted Jun 10, 2025·0 cites·20 claims
- 1484US2024258240A1Device and method of very high density routing used with embedded multi-die interconnect bridgeINTEL CORP·Filed 2024·Application pending·0 cites
- 1581US10103105B2High density organic bridge device and methodINTEL CORP·Filed 2016·Granted Oct 16, 2018·2 cites·20 claims
- 1680US11935805B2Package with underfill containment barrierINTEL CORP·Filed 2023·Granted Mar 19, 2024·0 cites·20 claims
- 1780US11443970B2Methods of forming a package substrateINTEL CORP·Filed 2020·Granted Sep 13, 2022·1 cites·7 claims
- 1879US10672713B2High density organic bridge device and methodINTEL CORP·Filed 2018·Granted Jun 2, 2020·1 cites·22 claims
- 1978US12040276B2Device and method of very high density routing used with embedded multi-die interconnect bridgeINTEL CORP·Filed 2022·Granted Jul 16, 2024·0 cites·20 claims
- 2077US11581271B2Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrateINTEL CORP·Filed 2019·Granted Feb 14, 2023·2 cites·27 claims
- 2177US11270959B2Enabling magnetic films in inductors integrated into semiconductor packagesINTEL CORP·Filed 2018·Granted Mar 8, 2022·3 cites·26 claims
- 2275US10978399B2Die interconnect substrate, an electrical device, and a method for forming a die interconnect substrateINTEL CORP·Filed 2017·Granted Apr 13, 2021·2 cites·25 claims
- 2374US9603247B2Electronic package with narrow-factor via including finish layerINTEL CORP·Filed 2014·Granted Mar 21, 2017·3 cites·18 claims
- 2473US12002762B2High density organic bridge device and methodINTEL CORP·Filed 2020·Granted Jun 4, 2024·0 cites·19 claims
- 2573US2025294781A1Magnetic core inductors on package substratesINTEL CORP·Filed 2025·Application pending·0 cites
- 2670US12336196B2Magnetic core inductors on package substratesINTEL CORP·Filed 2018·Granted Jun 17, 2025·1 cites·20 claims
- 2768US11552019B2Substrate patch reconstitution optionsINTEL CORP·Filed 2019·Granted Jan 10, 2023·1 cites·26 claims
- 2868US2023369192A1Dual trace thickness for single layer routingINTEL CORP·Filed 2023·Application pending·0 cites
- 2966US10980129B2Asymmetric electronic substrate and method of manufactureINTEL CORP·Filed 2020·Granted Apr 13, 2021·0 cites·10 claims
- 3059US2025210491A1Vertically embedded utility patch for semiconductor packagesINTEL CORP·Filed 2023·Application pending·0 cites
- 3157US9788416B2Multilayer substrate for semiconductor packagingINTEL CORP·Filed 2014·Granted Oct 10, 2017·1 cites·23 claims
- 3256US11508662B2Device and method of very high density routing used with embedded multi-die interconnect bridgeINTEL CORP·Filed 2016·Granted Nov 22, 2022·0 cites·14 claims
- 3355US10658198B2Solder resist layer structures for terminating de-featured components and methods of making the sameINTEL CORP·Filed 2019·Granted May 19, 2020·0 cites·15 claims
- 3454US2024113049A1Package substrate with open air gap structuresINTEL CORP·Filed 2022·Application pending·0 cites
- 3553US11769719B2Dual trace thickness for single layer routingINTEL CORP·Filed 2018·Granted Sep 26, 2023·0 cites·8 claims
- 3653US2025218911A1Electrolytic cobalt-iron-palladium-gold as a surface finish for embedded die attachmentsINTEL CORP·Filed 2023·Application pending·0 cites
- 3753US2025219002A1Electrolytic indium-palladium-gold as a surface finish for embedded die attachmentsINTEL CORP·Filed 2023·Application pending·0 cites
- 3852US2025218910A1Immersion gold-electroless palladium-immersion gold (igepig) as a surface finish for embedded die attachmentsINTEL CORP·Filed 2023·Application pending·0 cites
- 3952US2023317592A1Substrate with low-permittivity core and buildup layersINTEL CORP·Filed 2022·Application pending·0 cites
- 4052US2025218925A1Electroless nickel-electroless palladium-immersion gold (enepig) with thin nickel layer as a surface finish for embedded die attachmentsINTEL CORP·Filed 2023·Application pending·0 cites
- 4152US2025218924A1Electroless nickel-electroless palladium-immersion gold (enepig) as a surface finish for embedded die attachmentsINTEL CORP·Filed 2023·Application pending·0 cites
- 4251US12068172B2Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packagesINTEL CORP·Filed 2019·Granted Aug 20, 2024·0 cites·13 claims
- 4351US11923307B2Microelectronic structures including bridgesINTEL CORP·Filed 2020·Granted Mar 5, 2024·0 cites·18 claims
- 4449US7486161B2Reverse-phase cross coupling structureUNIVERSAL MICROWAVE TECHNOLOGY·Filed 2006·Granted Feb 3, 2009·2 cites·2 claims
- 4548US11764150B2Inductors for package substratesINTEL CORP·Filed 2019·Granted Sep 19, 2023·0 cites·18 claims
- 4647US2014342291A1Novel Dual-Tone Resist Formulations And MethodsUNIV TEXAS·Filed 2014·Application pending·0 cites
- 4746US2022199503A1Novel lga architecture for improving reliability performance of metal defined padsINTEL CORP·Filed 2020·Application pending·0 cites
- 4845US10244632B2Solder resist layer structures for terminating de-featured components and methods of making the sameINTEL CORP·Filed 2017·Granted Mar 26, 2019·0 cites·14 claims
- 4942US10916486B2Semiconductor device including silane based adhesion promoter and method of makingINTEL CORP·Filed 2016·Granted Feb 9, 2021·0 cites·14 claims
- 5041US2011262860A1Novel dual-tone resist formulations and methodsUNIV TEXAS·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →