Dual trace thickness for single layer routing

Abstract

Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

What is claimed is: 
     
         1 . A package substrate, comprising:
 a first conductive layer in a first dielectric;   a first trace of the first conductive layer having a first thickness; and   a second trace of the first conductive layer having a second thickness and a third thickness, wherein the third thickness of the second trace is greater than the first thickness of the first trace, and wherein the second thickness of the second trace is approximately equal to the first thickness of the first trace.   
     
     
         2 . The package substrate of  claim 1 , further comprising:
 a first via pad of the first conductive layer having the first thickness; and   a second via pad of the conductive layer having the second thickness and the third thickness, wherein the third thickness of the second via pad is greater than the first thickness of the first via pad, and wherein the second thickness of the second via pad is approximately equal to the first thickness of the first via pad.   
     
     
         3 . The package substrate of  claim 2 , further comprising:
 a second conductive layer on a top surface of a substrate;   a second dielectric on the second conductive layer, wherein the first dielectric is disposed on the second dielectric, wherein the substrate is at least one of a core substrate and a coreless substrate, and wherein the first conductive layer is disposed on the second dielectric; and   first vias in the second dielectric, wherein the first vias couple the second conductive layer to the first and second via pads of the first conductive layer.   
     
     
         4 . The package substrate of  claim 1 , wherein the first dielectric includes a first dielectric thickness and a second dielectric thickness, wherein the first dielectric thickness is defined by a top surface of the first dielectric and top surfaces of the first trace and the first via pad, and wherein the second dielectric thickness is defined by the top surface of the first dielectric and top surfaces of the second trace and the second via pad. 
     
     
         5 . The package substrate of  claim 4 , wherein the second dielectric thickness is less than the first dielectric thickness. 
     
     
         6 . The package substrate of  claim 4 , wherein the top surface of the second trace is above the top surface of the first trace, and wherein the top surface of the second via pad is above the top surface of the first via pad. 
     
     
         7 . The package substrate of  claim 2 , further comprising:
 a third via having a third thickness disposed on the first via pad having the first thickness, wherein the third via is disposed in the first dielectric; and   a fourth via having a fourth thickness disposed on the second via pad having the third thickness, wherein the fourth via is disposed in the first dielectric, wherein the third thickness is greater than the fourth thickness, wherein the third and fourth vias are tapered vias, wherein a bottom surface of the fourth via is above a bottom surface of the third via, and wherein the fourth thickness of the fourth via in the first dielectric is less than a thickness of the first vias in the second dielectric.   
     
     
         8 . The package substrate of  claim 2 , wherein the second via pad has a first diameter and a second diameter, wherein the first diameter is greater than the second diameter, wherein the first via pad has a third diameter, and wherein the third diameter of the first via pad is approximately equal to the second diameter, and wherein each of the second via pad and the second trace has an offsetting shape. 
     
     
         9 . The package substrate of  claim 1 , further comprising:
 a third conductive layer in a third dielectric;   a third via pad of the third conductive layer having a fifth thickness, wherein the fifth thickness of the third via pad is greater than the first thickness of the first trace and the first via pad of the first conductive layer, and wherein the fifth thickness of the third via pad is approximately equal to the third thickness of the second trace and the second via pad of the first conductive layer;   a fourth conductive layer on a bottom surface of the substrate;   a fourth dielectric on the fourth conductive layer, wherein the third dielectric is disposed on the fourth dielectric, and wherein the third conductive layer is disposed on the fourth dielectric; and   second vias in the fourth dielectric, wherein the second vias couple the fourth conductive layer to the third via pad of the third conductive layer.   
     
     
         10 . A semiconductor package, comprising:
 an interposer on a substrate;   a die on the interposer; and   a routing layer on the substrate, the routing layer comprising a conductive layer in a dielectric, a first trace of the conductive layer having a first thickness, and a second trace of the conductive layer having a second thickness, wherein the second thickness of the second trace is greater than the first thickness of the first trace.   
     
     
         11 . The semiconductor package of  claim 10 , further comprising:
 a first via pad of the conductive layer having the first thickness; and   a second via pad of the conductive layer having the second thickness, wherein the second thickness of the second via pad is greater than the first thickness of the first via pad.   
     
     
         12 . The semiconductor package of  claim 11 , further comprising:
 a first routing layer having a first conductive layer in a first dielectric, the routing layer disposed on the first routing layer, the dielectric disposed on the first dielectric, and the conductive layer disposed on the first dielectric; and   vias in the first dielectric, wherein the vias couple via pads of the first conductive layer to the first and second via pads of the conductive layer.   
     
     
         13 . The semiconductor package of  claim 10 , wherein the dielectric includes a first dielectric thickness and a second dielectric thickness, wherein the first dielectric thickness is defined by a top surface of the first trace and a top surface of the dielectric, and the second dielectric thickness is defined by a top surface of the second trace and the top surface of the dielectric. 
     
     
         14 . The semiconductor package of  claim 13 , wherein the second dielectric thickness is less than the first dielectric thickness. 
     
     
         15 . The semiconductor package of  claim 10 , wherein a top surface of the second trace is above a top surface of the first trace. 
     
     
         16 . The semiconductor package of  claim 11 , wherein a top surface of the second via pad is above a top surface of the first via pad. 
     
     
         17 . The semiconductor package of  claim 10 , wherein the first trace is a single-ended signal trace. 
     
     
         18 . The semiconductor package of  claim 17 , wherein the second trace is a differential signal trace. 
     
     
         19 . The semiconductor package of  claim 10 , wherein the second trace is a differential signal trace. 
     
     
         20 . The semiconductor package of  claim 11 , wherein the second via pad has a first diameter and a second diameter, the first diameter greater than the second diameter.