Inventor · disambiguated record
Wenhe Lin
Also filed as: LIN WENHE
28 granted patents·6 pending applications·836 citations·filing 2000–2018
97Inventor score
Files withCHARTERED SEMICONDUCTOR MFG23GLOBALFOUNDRIES INC3IBM3GLOBALFOUNDRIES SG PTE LTD2HO VINCENT1
Top patents by PatentIndex Score
34 records- 0198US6743291B2Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 1, 2004·125 cites·28 claims
- 0297US6475908B1Dual metal gate process: metals and their silicidesCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 5, 2002·128 cites·42 claims
- 0395US6458695B1Methods to form dual metal gates by incorporating metals and their conductive oxidesCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 1, 2002·83 cites·30 claims
- 0493US6664156B1Method for forming L-shaped spacers with precise width controlCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 16, 2003·76 cites·17 claims
- 0592US6486080B2Method to form zirconium oxide and hafnium oxide for high dielectric constant materialsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Nov 26, 2002·65 cites·20 claims
- 0691US7445978B2Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOSCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Nov 4, 2008·22 cites·31 claims
- 0791US6750519B2Dual metal gate process: metals and their silicidesCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 15, 2004·45 cites·8 claims
- 0888US6670248B1Triple gate oxide process with high-k gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 30, 2003·48 cites·15 claims
- 0987US6709912B1Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimizationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 23, 2004·53 cites·27 claims
- 1085US6534388B1Method to reduce variation in LDD series resistanceCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Mar 18, 2003·37 cites·10 claims
- 1184US7977185B2Method and apparatus for post silicide spacer removalIBM·Filed 2005·Granted Jul 12, 2011·9 cites·14 claims
- 1284US7256084B2Composite stress spacerCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Aug 14, 2007·12 cites·19 claims
- 1384US7005716B2Dual metal gate process: metals and their silicidesCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Feb 28, 2006·25 cites·4 claims
- 1483US6677652B2Methods to form dual metal gates by incorporating metals and their conductive oxidesCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jan 13, 2004·24 cites·4 claims
- 1578US6403425B1Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxideCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 11, 2002·25 cites·36 claims
- 1672US7993997B2Poly profile engineering to modulate spacer induced stress for device enhancementGLOBALFOUNDRIES SG PTE LTD·Filed 2007·Granted Aug 9, 2011·3 cites·24 claims
- 1771US8624329B2Spacer-less low-K dielectric processesLEE YONG MENG·Filed 2009·Granted Jan 7, 2014·5 cites·18 claims
- 1871US6891233B2Methods to form dual metal gates by incorporating metals and their conductive oxidesCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted May 10, 2005·15 cites·4 claims
- 1969US7999325B2Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOSGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Aug 16, 2011·3 cites·20 claims
- 2069US6524910B1Method of forming dual thickness gate dielectric structures via use of silicon nitride layersCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Feb 25, 2003·13 cites·14 claims
- 2168US7615427B2Spacer-less low-k dielectric processesCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Nov 10, 2009·3 cites·20 claims
- 2266US8148221B2Double anneal with improved reliability for dual contact etch stop liner schemeLIM KHEE YONG·Filed 2009·Granted Apr 3, 2012·3 cites·34 claims
- 2366US6835989B2Methods to form dual metal gates by incorporating metals and their conductive oxidesCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Dec 28, 2004·9 cites·4 claims
- 2461US7615433B2Double anneal with improved reliability for dual contact etch stop liner schemeCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Nov 10, 2009·1 cites·25 claims
- 2553US2008128834A1Hot carrier degradation reduction using ion implantation of silicon nitride layerIBM·Filed 2008·Application pending·0 cites
- 2652US2018233566A1Field effect transistor structure with recessed interlayer dielectric and methodGLOBALFOUNDRIES INC·Filed 2018·Application pending·0 cites
- 2751US10026818B1Field effect transistor structure with recessed interlayer dielectric and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 17, 2018·0 cites·16 claims
- 2848US2006151843A1Hot carrier degradation reduction using ion implantation of silicon nitride layerIBM·Filed 2005·Application pending·0 cites
- 2947US7022625B2Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetrationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Apr 4, 2006·4 cites·13 claims
- 3045US10347531B2Middle of the line (MOL) contact formation method and structureGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 9, 2019·0 cites·20 claims
- 3145US2009315115A1Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancementCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 3245US2008315317A1Semiconductor system having complementary strained channelsCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 3344US8519445B2Poly profile engineering to modulate spacer induced stress for device enhancementHO VINCENT·Filed 2011·Granted Aug 27, 2013·0 cites·20 claims
- 3440US2008124880A1Fet structure using disposable spacer and stress inducing layerCHARTERED SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →