Inventor · disambiguated record
William S. Graupp
Also filed as: GRAUPP WILLIAM S
10 granted patents·1 pending application·71 citations·filing 2005–2014
89Inventor score
Files withMENTOR GRAPHICS CORP6AVAGO TECHNOLOGIES GENERAL IP2BRUNET JEAN-MARIE2TORRES ROBLES JUAN ANDRES1
Top patents by PatentIndex Score
11 records- 0193US8056022B2Analysis optimizerMENTOR GRAPHICS CORP·Filed 2007·Granted Nov 8, 2011·15 cites·40 claims
- 0290US8832609B2Analysis optimizerMENTOR GRAPHICS CORP·Filed 2013·Granted Sep 9, 2014·5 cites·20 claims
- 0388US7208843B2Routing design to minimize electromigration damage to solder bumpsAVAGO TECHNOLOGIES GENERAL IP·Filed 2005·Granted Apr 24, 2007·21 cites·14 claims
- 0485US8504959B2Analysis optimizerTORRES ROBLES JUAN ANDRES·Filed 2011·Granted Aug 6, 2013·8 cites·25 claims
- 0577US7253528B2Trace design to minimize electromigration damage to solder bumpsAVAGO TECHNOLOGIES GENERAL IP·Filed 2005·Granted Aug 7, 2007·7 cites·12 claims
- 0675US8015510B2Interconnection modeling for semiconductor fabrication process effectsMENTOR GRAPHICS CORP·Filed 2007·Granted Sep 6, 2011·6 cites·40 claims
- 0770US7577932B2Gate modeling for semiconductor fabrication process effectsBRUNET JEAN-MARIE·Filed 2007·Granted Aug 18, 2009·5 cites·23 claims
- 0869US8813017B2Gate modeling for semiconductor fabrication process effectsBRUNET JEAN-MARIE·Filed 2011·Granted Aug 19, 2014·1 cites·31 claims
- 0968US8051393B2Gate modeling for semiconductor fabrication process effectsMENTOR GRAPHICS CORP·Filed 2009·Granted Nov 1, 2011·3 cites·20 claims
- 1049US9940428B2Hierarchical fill in a design layoutMENTOR GRAPHICS CORP·Filed 2014·Granted Apr 10, 2018·0 cites·18 claims
- 1142US2014201694A1Wrap Based Fill In Layout DesignsMENTOR GRAPHICS CORP·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →