Inventor · disambiguated record
William Matthew Hogan
Also filed as: HOGAN WILLIAM M · HOGAN WILLIAM MATTHEW
5 granted patents·7 pending applications·30 citations·filing 2003–2018
74Inventor score
Technology areasG06F
Top patents by PatentIndex Score
12 records- 0184US8516399B2Collaborative environment for physical verification of microdevice designsPARIS JAMES M·Filed 2010·Granted Aug 20, 2013·22 cites·20 claims
- 0267US10496783B2Context-aware pattern matching for layout processingMENTOR GRAPHICS CORP·Filed 2018·Granted Dec 3, 2019·1 cites·18 claims
- 0367US9135391B2Determination of electromigration susceptibility based on hydrostatic stress analysisMENTOR GRAPHICS CORP·Filed 2013·Granted Sep 15, 2015·2 cites·18 claims
- 0446US7239996B2Causality based event driven timing analysis engineBOLAND ARTHUR J·Filed 2003·Granted Jul 3, 2007·5 cites·31 claims
- 0545US2015143317A1Determination Of Electromigration FeaturesMENTOR GRAPHICS CORP·Filed 2013·Application pending·0 cites
- 0643US2015067621A1Logic-Driven Layout Pattern AnalysisMENTOR GRAPHICS CORP·Filed 2013·Application pending·0 cites
- 0740US2003220920A1Matching database fields in an electronic design automation environmentMENTOR GRAPHICS CORP·Filed 2003·Application pending·0 cites
- 0838US2017337300A1Logic-Driven Layout Pattern AnalysisMENTOR GRAPHICS CORP·Filed 2017·Application pending·0 cites
- 0936US9183330B2Estimation of power and thermal profilesHOGAN WILLIAM MATTHEW·Filed 2012·Granted Nov 10, 2015·0 cites·18 claims
- 1031US2012192134A1User Guided Short Correction And Schematic Fix VisualizationHOGAN WILLIAM MATTHEW·Filed 2011·Application pending·0 cites
- 1131US2011185323A1Stacked Integracted Circuit VerificationHOGAN WILLIAM MATTHEW·Filed 2010·Application pending·0 cites
- 1222US2011119544A1User Guided Short Correction And Schematic Fix VisualizationHOGAN WILLIAM MATTHEW·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →