Inventor · disambiguated record
Winston Lee
Also filed as: LEE WINSTON · LEE WINSTON DELANO
78 granted patents·4 pending applications·464 citations·filing 2001–2021
99Inventor score
Top patents by PatentIndex Score
82 records- 0195US7734966B1Method and system for memory testing and test data reporting during memory testingMARVELL INT LTD·Filed 2007·Granted Jun 8, 2010·41 cites·29 claims
- 0295US7609538B1Logic process DRAMMARVELL INT LTD·Filed 2006·Granted Oct 27, 2009·26 cites·30 claims
- 0394US10007521B1Banked physical register data flow architecture in out-of-order processorsMARVELL INT LTD·Filed 2016·Granted Jun 26, 2018·15 cites·20 claims
- 0494US8335878B2Multiport memory architecture, devices and systems including the same, and methods of using the sameLEE WINSTON·Filed 2009·Granted Dec 18, 2012·24 cites·20 claims
- 0593US9652246B1Banked physical register data flow architecture in out-of-order processorsMARVELL INT LTD·Filed 2013·Granted May 16, 2017·20 cites·20 claims
- 0692US8688877B1Multiport memory architectureMARVELL WORLD TRADE LTD·Filed 2012·Granted Apr 1, 2014·11 cites·15 claims
- 0792US8605534B2Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modesLEE WINSTON·Filed 2010·Granted Dec 10, 2013·17 cites·24 claims
- 0892US6527464B2Fingertip pen/stylusFiled 2001·Granted Mar 4, 2003·31 cites·12 claims
- 0991US8030128B1Method to form high density phase change memory (PCM) top contact every two bitsMARVELL INT LTD·Filed 2008·Granted Oct 4, 2011·21 cites·22 claims
- 1090US9570118B2Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modesMARVELL INT LTD·Filed 2015·Granted Feb 14, 2017·9 cites·16 claims
- 1190US8423841B1Method and systems for memory testing and test data reporting during memory testingLEE WINSTON·Filed 2011·Granted Apr 16, 2013·10 cites·19 claims
- 1289US8004926B2System and method for memory array decodingMARVELL WORLD TRADE LTD·Filed 2009·Granted Aug 23, 2011·13 cites·20 claims
- 1388US7939445B1High density via and metal interconnect structures, and methods of forming the sameMARVELL INT LTD·Filed 2008·Granted May 10, 2011·17 cites·21 claims
- 1487US7184290B1Logic process DRAMMARVELL INT LTD·Filed 2005·Granted Feb 27, 2007·16 cites·33 claims
- 1586US8999786B1Reducing source contact to gate spacing to decrease transistor pitchWU ALBERT·Filed 2008·Granted Apr 7, 2015·9 cites·20 claims
- 1685US7958413B1Method and system for memory testing and test data reporting during memory testingMARVELL INT LTD·Filed 2010·Granted Jun 7, 2011·7 cites·24 claims
- 1784US8947909B1System and method for creating a bipolar resistive RAM (RRAM)MARVELL INT LTD·Filed 2013·Granted Feb 3, 2015·7 cites·18 claims
- 1884US7571287B2Multiport memory architecture, devices and systems including the same, and methods of using the sameMARVELL WORLD TRADE LTD·Filed 2003·Granted Aug 4, 2009·25 cites·83 claims
- 1983US9142284B2Concurrent use of SRAM cells with both NMOS and PMOS pass gates in a memory systemMARVELL WORLD TRADE LTD·Filed 2013·Granted Sep 22, 2015·8 cites·20 claims
- 2083US8934285B2Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cellMARVELL WORLD TRADE LTD·Filed 2013·Granted Jan 13, 2015·6 cites·20 claims
- 2182US10056363B2Methods and systems to improve yield in multiple chips integration processesMARVELL WORLD TRADE LTD·Filed 2016·Granted Aug 21, 2018·2 cites·21 claims
- 2282US7745809B1Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench stripsMARVELL INT LTD·Filed 2008·Granted Jun 29, 2010·9 cites·19 claims
- 2381US9250992B1Test data reporting during memory testingMARVELL INT LTD·Filed 2014·Granted Feb 2, 2016·8 cites·22 claims
- 2479US8339195B2Circuits and methods for calibrating offset in an amplifierLEE WINSTON·Filed 2010·Granted Dec 25, 2012·6 cites·20 claims
- 2578US6570781B1Logic process DRAMMARVELL INT LTD·Filed 2001·Granted May 27, 2003·24 cites·51 claims
- 2677US7888166B2Method to form high efficiency GST cell using a double heater cutMARVELL WORLD TRADE LTD·Filed 2010·Granted Feb 15, 2011·3 cites·9 claims
- 2775US9218856B2Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modesMARVELL INT LTD·Filed 2013·Granted Dec 22, 2015·4 cites·12 claims
- 2875US8885388B2Apparatus and method for reforming resistive memory cellsMARVELL WORLD TRADE LTD·Filed 2013·Granted Nov 11, 2014·4 cites·21 claims
- 2974US9047252B1Method and apparatus for detecting a row or a column of a memory to repair without reporting all corresponding defective memory cellsMARVELL INT LTD·Filed 2014·Granted Jun 2, 2015·3 cites·20 claims
- 3074US8762801B1Method and system for detecting and repairing defective memory cells without reporting a defective memory cellMARVELL INT LTD·Filed 2013·Granted Jun 24, 2014·3 cites·20 claims
- 3174US7709835B2Method to form high efficiency GST cell using a double heater cutMARVELL WORLD TRADE LTD·Filed 2008·Granted May 4, 2010·3 cites·7 claims
- 3273US11196587B2Permutated ring networkDEGIRUM CORP·Filed 2017·Granted Dec 7, 2021·2 cites·22 claims
- 3373US10319727B2Fabricating memory devices with optimized gate oxide thicknessMARVELL WORLD TRADE LTD·Filed 2017·Granted Jun 11, 2019·1 cites·7 claims
- 3472US7807539B1Ion implantation and process sequence to form smaller base pick-upMARVELL INT LTD·Filed 2008·Granted Oct 5, 2010·4 cites·10 claims
- 3571US10884451B2System and methods for completing a cascaded clock ring busDEGIRUM CORP·Filed 2018·Granted Jan 5, 2021·1 cites·33 claims
- 3671US7839672B1Phase change memory array circuits and methods of manufactureMARVELL INT LTD·Filed 2007·Granted Nov 23, 2010·6 cites·45 claims
- 3770US9214230B2Resistive random access memory cell structure with reduced programming voltageMARVELL WORLD TRADE LTD·Filed 2015·Granted Dec 15, 2015·2 cites·20 claims
- 3870US7985616B1Methods to form wide heater trenches and to form memory cells to engage heatersMARVELL INT LTD·Filed 2008·Granted Jul 26, 2011·3 cites·11 claims
- 3968US10476656B2System and method for asynchronous, multiple clock domain data streams coalescing and resynchronizationDEGIRUM CORP·Filed 2018·Granted Nov 12, 2019·1 cites·23 claims
- 4068US9245961B1Reducing source contact to gate spacing to decrease transistor pitchMARVELL INT LTD·Filed 2015·Granted Jan 26, 2016·1 cites·20 claims
- 4167US9490427B2Resistive random access memory cell structureMARVELL WORLD TRADE LTD·Filed 2015·Granted Nov 8, 2016·1 cites·22 claims
- 4267US9147837B1Resistive memory cell and method for forming a resistive memory cellMARVELL INT LTD·Filed 2015·Granted Sep 29, 2015·2 cites·18 claims
- 4367US9047945B2Systems and methods for reading resistive random access memory (RRAM) cellsMARVELL WORLD TRADE LTD·Filed 2013·Granted Jun 2, 2015·3 cites·20 claims
- 4467US7863709B1Low base resistance bipolar junction transistor arrayMARVELL INT LTD·Filed 2008·Granted Jan 4, 2011·2 cites·15 claims
- 4566US10896900B2Methods and systems for packaging an integrated circuitMARVELL ASIA PTE LTD·Filed 2019·Granted Jan 19, 2021·0 cites·20 claims
- 4665US8451041B2Charge-injection sense-amp logicSU JASON T·Filed 2011·Granted May 28, 2013·3 cites·18 claims
- 4764US7994052B1High-density patterningMARVELL INT LTD·Filed 2008·Granted Aug 9, 2011·2 cites·17 claims
- 4864US6947324B1Logic process DRAMMARVELL INT LTD·Filed 2003·Granted Sep 20, 2005·11 cites·42 claims
- 4963US12455746B2Method and apparatus for performing matrix multiplicationDEGIRUM CORP·Filed 2021·Granted Oct 28, 2025·0 cites·24 claims
- 5062US10431574B2Methods and systems for packaging semiconductor devices to improve yieldMARVELL WORLD TRADE LTD·Filed 2018·Granted Oct 1, 2019·0 cites·19 claims
Showing the top 50 of 82 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Winston Lee files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →