Inventor · disambiguated record
William A. Shelly
Also filed as: PORTER MARION G · SHELLY WILLIAM A
35 granted patents·1 pending application·1,011 citations·filing 1975–2003
98Inventor score
Technology areasG06F
Files withBULL HN INFORMATION SYST18HONEYWELL INF SYSTEMS12BULL INFORMATION SYSTEMS INC2HONEYWELL BULL1WILHITE JOHN E1
Top patents by PatentIndex Score
36 records- 0189US4521851ACentral processorHONEYWELL INF SYSTEMS·Filed 1982·Granted Jun 4, 1985·96 cites·6 claims
- 0284US6223228B1Apparatus for synchronizing multiple processors in a data processing systemBULL HN INFORMATION SYST·Filed 1998·Granted Apr 24, 2001·110 cites·12 claims
- 0382US4006466AProgrammable interface apparatus and methodHONEYWELL INF SYSTEMS·Filed 1975·Granted Feb 1, 1977·47 cites·24 claims
- 0480US6530076B1Data processing system processor dynamic selection of internal signal tracingBULL HN INFORMATION SYST·Filed 1999·Granted Mar 4, 2003·102 cites·19 claims
- 0579US4594659AMethod and apparatus for prefetching instructions for a central execution pipeline unitHONEYWELL INF SYSTEMS·Filed 1982·Granted Jun 10, 1986·70 cites·20 claims
- 0677US4208716ACache arrangement for performing simultaneous read/write operationsHONEYWELL INF SYSTEMS·Filed 1978·Granted Jun 17, 1980·38 cites·39 claims
- 0774US4371927AData processing system programmable pre-read capabilityHONEYWELL INF SYSTEMS·Filed 1980·Granted Feb 1, 1983·43 cites·36 claims
- 0874US4245304ACache arrangement utilizing a split cycle mode of operationHONEYWELL INF SYSTEMS·Filed 1978·Granted Jan 13, 1981·33 cites·39 claims
- 0973US4521850AInstruction buffer associated with a cache memory unitHONEYWELL INF SYSTEMS·Filed 1982·Granted Jun 4, 1985·42 cites·7 claims
- 1073US4217640ACache unit with transit block buffer apparatusHONEYWELL INF SYSTEMS·Filed 1978·Granted Aug 12, 1980·31 cites·37 claims
- 1171US5649090AFault tolerant multiprocessor computer systemBULL HN INFORMATION SYST·Filed 1991·Granted Jul 15, 1997·67 cites·3 claims
- 1270US4602368ADual validity bit arraysHONEYWELL INF SYSTEMS·Filed 1983·Granted Jul 22, 1986·41 cites·11 claims
- 1368US4000487ASteering code generating apparatus for use in an input/output processing systemHONEYWELL INF SYSTEMS·Filed 1975·Granted Dec 28, 1976·29 cites·22 claims
- 1468US3976977AProcessor for input-output processing systemHONEYWELL INF SYSTEMS·Filed 1975·Granted Aug 24, 1976·31 cites·8 claims
- 1564US6898738B2High integrity cache directoryBULL HN INFORMATION SYST·Filed 2001·Granted May 24, 2005·14 cites·8 claims
- 1657US6754859B2Computer processor read/alter/rewrite optimization cache invalidate signalsBULL HN INFORMATION SYST·Filed 2001·Granted Jun 22, 2004·6 cites·12 claims
- 1757US4471432AMethod and apparatus for initiating the execution of instructions using a central pipeline execution unitWILHITE JOHN E·Filed 1982·Granted Sep 11, 1984·25 cites·10 claims
- 1849US6230263B1Data processing system processor delay instructionFiled 1998·Granted May 8, 2001·22 cites·24 claims
- 1947US5251321ABinary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unitBULL HN INFORMATION SYST·Filed 1992·Granted Oct 5, 1993·20 cites·4 claims
- 2046US6249880B1Method and apparatus for exhaustively testing interactions among multiple processorsBULL HN INFORMATION SYST·Filed 1998·Granted Jun 19, 2001·18 cites·21 claims
- 2145US5263034AError detection in the basic processing unit of a VLSI central processorBULL INFORMATION SYSTEMS INC·Filed 1990·Granted Nov 16, 1993·19 cites·5 claims
- 2244US6052700ACalendar clock caching in a multiprocessor data processing systemBULL HN INFORMATION SYST·Filed 1998·Granted Apr 18, 2000·16 cites·20 claims
- 2344US5276862ASafestore frame implementation in a central processorBULL HN INFORMATION SYST·Filed 1991·Granted Jan 4, 1994·16 cites·5 claims
- 2443US6006309AInformation block transfer management in a multiprocessor computer system employing private caches for individual center processor units and a shared cacheBULL HN INFORMATION SYST·Filed 1996·Granted Dec 21, 1999·18 cites·5 claims
- 2542US6970977B2Equal access to prevent gateword dominance in a multiprocessor write-into-cache environmentBULL HN INFORMATION SYST·Filed 2003·Granted Nov 29, 2005·0 cites·6 claims
- 2642US5829029APrivate cache miss and access management in a multiprocessor system with shared memoryBULL HN INFORMATION SYST·Filed 1996·Granted Oct 27, 1998·17 cites·3 claims
- 2741US2004111656A1Computer processor read/alter/rewrite optimization cache invalidate signalsFiled 2003·Application pending·0 cites
- 2835US6484272B1Gate close balking for fair gating in a nonuniform memory architecture data processing systemBULL HN INFORMATION SYST·Filed 1999·Granted Nov 19, 2002·8 cites·13 claims
- 2935US3990051AMemory steering in a data processing systemHONEYWELL INF SYSTEMS·Filed 1975·Granted Nov 2, 1976·5 cites·3 claims
- 3034US5644761ABasic operations synchronization and local mode controller in a VLSI central processorBULL HN INFORMATION SYST·Filed 1992·Granted Jul 1, 1997·7 cites·9 claims
- 3131US5963973AMultiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of changeable dataBULL HN INFORMATION SYST·Filed 1997·Granted Oct 5, 1999·9 cites·10 claims
- 3231US5515529ACentral processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit conductor countBULL HN INFORMATION SYST·Filed 1994·Granted May 7, 1996·3 cites·5 claims
- 3331US4858176ADistributor of machine words between units of a central processorHONEYWELL BULL·Filed 1988·Granted Aug 15, 1989·3 cites·6 claims
- 3430US5495579ACentral processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor countBULL HN INFORMATION SYST·Filed 1994·Granted Feb 27, 1996·2 cites·5 claims
- 3528US6480973B1Gate close failure notification for fair gating in a nonuniform memory architecture data processing systemBULL INFORMATION SYSTEMS INC·Filed 1999·Granted Nov 12, 2002·1 cites·6 claims
- 3623US6351807B1Data processing system utilizing multiple resister loading for fast domain switchingBULL HN INFORMATION SYST·Filed 1998·Granted Feb 26, 2002·2 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →