Computer processor read/alter/rewrite optimization cache invalidate signals

Abstract

A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.

What is claimed is:  
     
         1 . A processor comprising: 
 A) a first register;    B) a means for decoding a Wait for Change instruction; and    C) a means for executing a Wait for Change instruction in response to decoding the Wait for Change instruction, wherein: 
 execution of the Wait for Change instruction terminates when either a contents of a specified location in a memory differs from a contents of the first register or a specified time period has elapsed.  
   
     
     
         2 . The processor in  claim 1  wherein: 
 means (C) comprises: 
 1) a means for comparing the specified location in the memory to the contents of the first register;  
 2) a means for receiving a cache invalidate signal; and  
 3) a means for waiting for the cache invalidate signal for a cache line that includes the specified location in the memory when the comparing in means (1) fails.  
 
 
     
     
         3 . A processor comprising: 
 A) a means for decoding a Lock instruction; and    B) a means for executing a Lock instruction in response to decoding the Lock instruction, wherein: 
 execution of the Lock instruction terminates when either a lock value is written to a specified location in a memory overwriting a non-lock value in the specified location or a specified time period has elapsed.  
   
     
     
         4 . The processor in  claim 3  wherein: means (B) comprises: 
 1) a means for testing the specified location in the memory for containing the non-lock value;  
 2) a means for writing the lock value to the specified location in the memory when the specified location in the memory contains the non-lock value; 
 3) a means for receiving a cache invalidate signal; and  
 4) a means for waiting for the cache invalidate signal for a cache line that includes the specified location in the memory when the testing in means (1) fails.