Inventor · disambiguated record
William L. Walker
Also filed as: WALKER WILLIAM · WALKER WILLIAM L · WALKER WILLIAM LOUIE
33 granted patents·11 pending applications·65 citations·filing 1994–2024
95Inventor score
Top patents by PatentIndex Score
44 records- 0198US11868777B2Processor-guided execution of offloaded instructions using fixed function operationsADVANCED MICRO DEVICES INC·Filed 2020·Granted Jan 9, 2024·12 cites·20 claims
- 0295US12153926B2Processor-guided execution of offloaded instructions using fixed function operationsADVANCED MICRO DEVICES INC·Filed 2023·Granted Nov 26, 2024·3 cites·20 claims
- 0387US10282295B1Reducing cache footprint in cache coherence directoryADVANCED MICRO DEVICES INC·Filed 2017·Granted May 7, 2019·5 cites·20 claims
- 0486US12306754B2Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in cachesADVANCED MICRO DEVICES INC·Filed 2022·Granted May 20, 2025·1 cites·20 claims
- 0585US9946646B2Systems and method for delayed cache utilizationADVANCED MICRO DEVICES INC·Filed 2016·Granted Apr 17, 2018·4 cites·28 claims
- 0684US10073776B2Shadow tag memory to monitor state of cachelines at different cache levelADVANCED MICRO DEVICES INC·Filed 2016·Granted Sep 11, 2018·4 cites·22 claims
- 0782US10705958B2Coherency directory entry allocation based on eviction costsADVANCED MICRO DEVICES INC·Filed 2018·Granted Jul 7, 2020·3 cites·22 claims
- 0882US9864681B2Dynamic multithreaded cache allocationADVANCED MICRO DEVICES INC·Filed 2016·Granted Jan 9, 2018·3 cites·20 claims
- 0980US9529719B2Dynamic multithreaded cache allocationWALKER WILLIAM L·Filed 2012·Granted Dec 27, 2016·6 cites·20 claims
- 1078US11294810B2Memory request throttling to constrain memory bandwidth utilizationADVANCED MICRO DEVICES INC·Filed 2017·Granted Apr 5, 2022·2 cites·22 claims
- 1178US10956332B2Retaining cache entries of a processor core during a powered-down stateADVANCED MICRO DEVICES INC·Filed 2017·Granted Mar 23, 2021·2 cites·20 claims
- 1272US10289567B2Systems and method for delayed cache utilizationADVANCED MICRO DEVICES INC·Filed 2018·Granted May 14, 2019·1 cites·24 claims
- 1369US11675703B2Memory request throttling to constrain memory bandwidth utilizationADVANCED MICRO DEVICES INC·Filed 2022·Granted Jun 13, 2023·0 cites·22 claims
- 1468US12455823B2Super-temporal cache replacement policyADVANCED MICRO DEVICES INC·Filed 2023·Granted Oct 28, 2025·0 cites·20 claims
- 1567US8791713B2Method and apparatus for bypassing silicon bugsWALKER WILLIAM L·Filed 2010·Granted Jul 29, 2014·2 cites·20 claims
- 1666US12367145B2Remote acceleration for data dependent address calculationADVANCED MICRO DEVICES INC·Filed 2023·Granted Jul 22, 2025·0 cites·20 claims
- 1764US12430257B2Smart cache cleanerADVANCED MICRO DEVICES INC·Filed 2023·Granted Sep 30, 2025·0 cites·20 claims
- 1864US11704248B2Retaining cache entries of a processor core during a powered-down stateADVANCED MICRO DEVICES INC·Filed 2020·Granted Jul 18, 2023·0 cites·20 claims
- 1963US9262322B2Method and apparatus for storing a processor architectural state in cache memoryADVANCED MICRO DEVICES INC·Filed 2013·Granted Feb 16, 2016·1 cites·19 claims
- 2063US2022100686A1Probe interrupt deliveryADVANCED MICRO DEVICES INC·Filed 2021·Application pending·0 cites
- 2161US11847062B2Re-fetching data for L3 cache data evictions into a last-level cacheADVANCED MICRO DEVICES INC·Filed 2021·Granted Dec 19, 2023·0 cites·20 claims
- 2257US11829196B2Ring transport employing clock wake suppressionADVANCED MICRO DEVICES INC·Filed 2019·Granted Nov 28, 2023·0 cites·20 claims
- 2354US10740029B2Expandable buffer for memory transactionsADVANCED MICRO DEVICES INC·Filed 2017·Granted Aug 11, 2020·0 cites·20 claims
- 2453US11210246B2Probe interrupt deliveryADVANCED MICRO DEVICES INC·Filed 2018·Granted Dec 28, 2021·0 cites·17 claims
- 2553US2025045206A1Bloom-based hit predictorADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 2652US2025307162A1Cache Data Distribution for a Stacked Die ConfigurationADVANCED MICRO DEVICES INC·Filed 2024·Application pending·0 cites
- 2751US2024220409A1Unified flexible cacheADVANCED MICRO DEVICES INC·Filed 2022·Application pending·0 cites
- 2850US11561906B2Rinsing cache lines from a common memory page to memoryADVANCED MICRO DEVICES INC·Filed 2017·Granted Jan 24, 2023·0 cites·19 claims
- 2950US11226900B2Using a bloom filter to reduce the number of memory addressees tracked by a coherence directoryADVANCED MICRO DEVICES INC·Filed 2020·Granted Jan 18, 2022·0 cites·18 claims
- 3050US10366027B2I/O writes with cache steeringADVANCED MICRO DEVICES INC·Filed 2017·Granted Jul 30, 2019·0 cites·25 claims
- 3150US9916243B2Method and apparatus for performing a bus lock and translation lookaside buffer invalidationADVANCED MICRO DEVICES INC·Filed 2014·Granted Mar 13, 2018·0 cites·18 claims
- 3248US9317100B2Accelerated cache rinse when preparing a power state transitionADVANCED MICRO DEVICES INC·Filed 2013·Granted Apr 19, 2016·0 cites·23 claims
- 3346US9940247B2Concurrent access to cache dirty bitsWALKER WILLIAM L·Filed 2012·Granted Apr 10, 2018·0 cites·14 claims
- 3446US2015095586A1Storing non-temporal cache dataADVANCED MICRO DEVICES INC·Filed 2013·Application pending·0 cites
- 3543US8909867B2Method and apparatus for allocating instruction and data for a unified cacheWALKER WILLIAM L·Filed 2010·Granted Dec 9, 2014·0 cites·17 claims
- 3643US2013311724A1Cache system with biased cache line replacement policy and method thereforWALKER WILLIAM L·Filed 2012·Application pending·0 cites
- 3742US2014108734A1Method and apparatus for saving processor architectural state in cache hierarchyADVANCED MICRO DEVICES INC·Filed 2012·Application pending·0 cites
- 3842US2014189265A1Atomic time counter synchronizationADVANCED MICRO DEVICES INC·Filed 2012·Application pending·0 cites
- 3940US9043628B2Power management of multiple compute units sharing a cacheKITCHIN PAUL·Filed 2012·Granted May 26, 2015·0 cites·29 claims
- 4040US2013346683A1Cache Sector Dirty BitsWALKER WILLIAM L·Filed 2012·Application pending·0 cites
- 4139US2017357585A1Setting cache entry age based on hints from another cache levelADVANCED MICRO DEVICES INC·Filed 2016·Application pending·0 cites
- 4238US2012054439A1Method and apparatus for allocating cache bandwidth to multiple processorsWALKER WILLIAM L·Filed 2010·Application pending·0 cites
- 4337US5623616AFloating point operaton throughput controlHEWLETT PACKARD CO·Filed 1994·Granted Apr 22, 1997·10 cites·18 claims
- 4430US5829049ASimultaneous execution of two memory reference instructions with only one address calculationHEWLETT PACKARD CO·Filed 1997·Granted Oct 27, 1998·6 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →