Inventor · disambiguated record
Xiaoqing Wen
Also filed as: WEN XIAOQING
44 granted patents·6 pending applications·783 citations·filing 2002–2022
98Inventor score
Files withSYNTEST TECHNOLOGIES INC29JAPAN SCIENCE & TECH AGENCY4KYUSHU INST TECHNOLOGY3MIYASE KOHEI3TENCENT TECH SHENZHEN CO LTD3
Top patents by PatentIndex Score
50 records- 0196US7412672B1Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Aug 12, 2008·36 cites·58 claims
- 0296US7058869B2Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Jun 6, 2006·119 cites·34 claims
- 0395US7032148B2Mask network design for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Apr 18, 2006·84 cites·76 claims
- 0494US7284175B2Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniquesSYNTEST TECHNOLOGIES INC·Filed 2006·Granted Oct 16, 2007·30 cites·27 claims
- 0594US6954887B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Oct 11, 2005·64 cites·33 claims
- 0693US8775985B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jul 8, 2014·7 cites·2 claims
- 0793US7007213B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Feb 28, 2006·52 cites·30 claims
- 0893US6957403B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Oct 18, 2005·69 cites·68 claims
- 0992US7904857B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2007·Granted Mar 8, 2011·20 cites·12 claims
- 1091US7191373B2Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniquesSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Mar 13, 2007·48 cites·19 claims
- 1189US8219945B2Computer-aided design system to automate scan synthesis at register-transfer levelWANG LAUNG-TERNG·Filed 2011·Granted Jul 10, 2012·5 cites·4 claims
- 1288US7331032B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Feb 12, 2008·12 cites·11 claims
- 1387US7945830B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2010·Granted May 17, 2011·5 cites·30 claims
- 1487US7512851B2Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Mar 31, 2009·39 cites·46 claims
- 1586US7552373B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Jun 23, 2009·36 cites·44 claims
- 1686US7260756B1Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-testSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Aug 21, 2007·11 cites·79 claims
- 1784US7124342B2Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Oct 17, 2006·31 cites·102 claims
- 1883US9678156B2Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECH INC·Filed 2016·Granted Jun 13, 2017·3 cites·20 claims
- 1983US7779322B1Compacting test responses using X-driven compactorSYNTEST TECHNOLOGIES INC·Filed 2007·Granted Aug 17, 2010·12 cites·12 claims
- 2082US7451371B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Nov 11, 2008·9 cites·33 claims
- 2182US7434126B2Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faultsSYNTEST TECHNOLOGIES INC·Filed 2007·Granted Oct 7, 2008·8 cites·7 claims
- 2281US12318692B2Virtual object control method and apparatus, terminal, and storage mediumTENCENT TECH SHENZHEN CO LTD·Filed 2022·Granted Jun 3, 2025·1 cites·20 claims
- 2381US7747920B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Jun 29, 2010·8 cites·24 claims
- 2479US7743306B2Test vector generating method and test vector generating program of semiconductor logic circuit deviceKYUSHU INST TECHNOLOGY·Filed 2006·Granted Jun 22, 2010·10 cites·16 claims
- 2579US7735049B2Mask network design for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2006·Granted Jun 8, 2010·8 cites·38 claims
- 2678US7444567B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Oct 28, 2008·17 cites·18 claims
- 2777US7962822B2Generating device, generating method, program and recording mediumJAPAN SCIENCE & TECH AGENCY·Filed 2008·Granted Jun 14, 2011·9 cites·19 claims
- 2875US7779323B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Aug 17, 2010·5 cites·21 claims
- 2968US7904773B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Mar 8, 2011·4 cites·34 claims
- 3064US8543950B2Computer-aided design system to automate scan synthesis at register-transfer levelWANG LAUNG-TERNG L-T·Filed 2012·Granted Sep 24, 2013·1 cites·4 claims
- 3164US7979765B2Generating device, generating method, program and recording mediumJAPAN SCIENCE & TECH AGENCY·Filed 2007·Granted Jul 12, 2011·6 cites·10 claims
- 3263US8001437B2Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuitKYUSHU INST TECHNOLOGY·Filed 2008·Granted Aug 16, 2011·4 cites·3 claims
- 3361US7478295B2Method and apparatus of fault diagnosis for integrated logic circuitsKYUSHU INST TECHNOLOGY·Filed 2005·Granted Jan 13, 2009·3 cites·17 claims
- 3459US9316688B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-testSYNTEST TECHNOLOGIES INC·Filed 2015·Granted Apr 19, 2016·0 cites·36 claims
- 3559US9274168B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-testSYNTEST TECHNOLOGIES INC·Filed 2015·Granted Mar 1, 2016·0 cites·30 claims
- 3659US7721173B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2009·Granted May 18, 2010·3 cites·47 claims
- 3758US7971118B2Conversion device, conversion method, program, and recording mediumJAPAN SCIENCE & TECH AGENCY·Filed 2008·Granted Jun 28, 2011·3 cites·15 claims
- 3857US9091730B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jul 28, 2015·0 cites·84 claims
- 3953US9696377B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECH INC·Filed 2015·Granted Jul 4, 2017·0 cites·12 claims
- 4048US7913144B2Diagnostic device, diagnostic method, program, and recording mediumJAPAN SCIENCE & TECH AGENCY·Filed 2007·Granted Mar 22, 2011·1 cites·13 claims
- 4147US2008276141A1Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2008·Application pending·0 cites
- 4245US2023037089A1Operation control method and apparatus, storage medium, and electronic deviceTENCENT TECH SHENZHEN CO LTD·Filed 2022·Application pending·0 cites
- 4345US2023014355A1Human-computer interaction interface control method and apparatus, computer device, and storage mediumTENCENT TECH SHENZHEN CO LTD·Filed 2022·Application pending·0 cites
- 4443US8589751B2Don't-care-bit identification method and don't-care-bit identification programMIYASE KOHEI·Filed 2010·Granted Nov 19, 2013·0 cites·6 claims
- 4537US2011209024A1Generation device, classification method, generation method, and programKYUSHU INST OF TEHNOLOGY·Filed 2009·Application pending·0 cites
- 4635US2004153926A1Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuitFiled 2003·Application pending·0 cites
- 4732US8429472B2Generating device, generating method, and programMIYASE KOHEI·Filed 2009·Granted Apr 23, 2013·0 cites·7 claims
- 4831US8117513B2Test method and test program of semiconductor logic circuit deviceWEN XIAOQING·Filed 2006·Granted Feb 14, 2012·0 cites·16 claims
- 4930US8453023B2Target logic value determination method for unspecified bit in test vector for combinational circuit and non-transitory computer-readable mediumMIYASE KOHEI·Filed 2010·Granted May 28, 2013·0 cites·6 claims
- 5030US2002194558A1Method and system to optimize test cost and disable defects for scan and BIST memoriesFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →