Inventor · disambiguated record
Yael Kinderman
Also filed as: KINDERMAN YAEL
14 granted patents·95 citations·filing 2006–2019
91Inventor score
Top patents by PatentIndex Score
14 records- 0191US10607039B1Constrained metric optimization of a system on chipCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Mar 31, 2020·15 cites·18 claims
- 0289US9891281B1Method and system for automatically identifying test runs contributing to coverage events of interest in verification test dataCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Feb 13, 2018·7 cites·11 claims
- 0389US9582620B1Method and system for automated refined exclusion of entities from a metric driven verification analysis scoreCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Feb 28, 2017·10 cites·20 claims
- 0486US10108514B1Method and system for performing regression session on a device under testCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 23, 2018·7 cites·20 claims
- 0583US7870523B1System and method for test generation with dynamic constraints using static analysis and multidomain constraint reductionCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jan 11, 2011·20 cites·28 claims
- 0682US10586014B1Method and system for verification using combined verification dataCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 10, 2020·6 cites·16 claims
- 0780US9514035B1Coverage driven generation of constrained random stimuliCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 6, 2016·8 cites·17 claims
- 0878US10423741B1Constrained metric verification analysis of a system on chipCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Sep 24, 2019·3 cites·19 claims
- 0976US10394699B1Method and system for reusing a refinement file in coverage gradingCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Aug 27, 2019·4 cites·12 claims
- 1076US8903823B1Coverage-based bug clusteringMEIR RESHEF·Filed 2011·Granted Dec 2, 2014·7 cites·27 claims
- 1171US9824175B1Method and system of evaluation of validity of a refinement rule for a hardware emulationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 21, 2017·2 cites·20 claims
- 1268US9582458B2Generation of a random sub-space of the space of assignments for a set of generative attributes for verification coverage closureCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Feb 28, 2017·2 cites·20 claims
- 1368US9208271B1Transaction correlation systemMEIR RESHEF·Filed 2010·Granted Dec 8, 2015·4 cites·32 claims
- 1449US11868241B1Method and system for optimizing a verification test regressionCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jan 9, 2024·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →