Inventor · disambiguated record
Yann Mignot
Also filed as: MIGNOT YANN · MIGNOT YANN A M
28 granted patents·15 pending applications·67 citations·filing 2014–2023
95Inventor score
Files withIBM34TESSERA INC4ELPIS TECH INC2ADEIA SEMICONDUCTOR SOLUTIONS LLC1ST MICROELECTRONICS INC1
Top patents by PatentIndex Score
43 records- 0197US9991156B2Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogsIBM·Filed 2016·Granted Jun 5, 2018·15 cites·6 claims
- 0296US11610780B2Alternating hardmasks for tight-pitch line formationTESSERA LLC·Filed 2021·Granted Mar 21, 2023·2 cites·20 claims
- 0396US9691659B1Via and chamfer control for advanced interconnectsIBM·Filed 2016·Granted Jun 27, 2017·14 cites·20 claims
- 0492US9607886B1Self aligned conductive lines with relaxed overlayIBM·Filed 2016·Granted Mar 28, 2017·6 cites·20 claims
- 0589US9786554B1Self aligned conductive linesIBM·Filed 2016·Granted Oct 10, 2017·5 cites·7 claims
- 0688US10090378B1Efficient metal-insulator-metal capacitorIBM·Filed 2017·Granted Oct 2, 2018·4 cites·5 claims
- 0788US9773700B1Aligning conductive vias with trenchesIBM·Filed 2016·Granted Sep 26, 2017·5 cites·9 claims
- 0887US11031248B2Alternating hardmasks for tight-pitch line formationTESSERA INC·Filed 2019·Granted Jun 8, 2021·2 cites·21 claims
- 0987US10546774B2Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogsIBM·Filed 2018·Granted Jan 28, 2020·3 cites·9 claims
- 1087US10475905B2Techniques for vertical FET gate length controlIBM·Filed 2018·Granted Nov 12, 2019·4 cites·18 claims
- 1185US12322601B2Alternating hardmasks for tight-pitch line formationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Jun 3, 2025·0 cites·22 claims
- 1283US10580652B2Alternating hardmasks for tight-pitch line formationIBM·Filed 2018·Granted Mar 3, 2020·2 cites·20 claims
- 1377US10957583B2Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogsIBM·Filed 2019·Granted Mar 23, 2021·1 cites·19 claims
- 1476US9852946B1Self aligned conductive linesIBM·Filed 2016·Granted Dec 26, 2017·2 cites·20 claims
- 1575US10651266B2Efficient metal-insulator-metal capacitorTESSERA INC·Filed 2018·Granted May 12, 2020·1 cites·17 claims
- 1673US9911647B2Self aligned conductive linesIBM·Filed 2017·Granted Mar 6, 2018·1 cites·20 claims
- 1770US10978550B2Efficient metal-insulator-metal capacitorTESSERA INC·Filed 2020·Granted Apr 13, 2021·0 cites·17 claims
- 1867US11171002B2Alternating hardmasks for tight-pitch line formationTESSERA INC·Filed 2020·Granted Nov 9, 2021·0 cites·16 claims
- 1962US10978576B2Techniques for vertical FET gate length controlELPIS TECH INC·Filed 2019·Granted Apr 13, 2021·0 cites·19 claims
- 2062US10395985B2Self aligned conductive lines with relaxed overlayIBM·Filed 2018·Granted Aug 27, 2019·0 cites·19 claims
- 2159US10256289B2Efficient metal-insulator-metal capacitor fabricationIBM·Filed 2017·Granted Apr 9, 2019·0 cites·12 claims
- 2258US10714389B2Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integrationELPIS TECH INC·Filed 2019·Granted Jul 14, 2020·0 cites·20 claims
- 2358US10083864B2Self aligned conductive lines with relaxed overlayIBM·Filed 2017·Granted Sep 25, 2018·0 cites·11 claims
- 2457US11164772B2Spacer-defined process for lithography-etch double patterning for interconnectsIBM·Filed 2018·Granted Nov 2, 2021·0 cites·8 claims
- 2557US2024312839A1Fully aligned via to single damascene upper trenchIBM·Filed 2023·Application pending·0 cites
- 2657US2024282704A1Subtractive metal via with metal bridgeIBM·Filed 2023·Application pending·0 cites
- 2757US2025006658A1Three Dimensional Crackstop Interweave Architectural Design Using Supervia.IBM·Filed 2023·Application pending·0 cites
- 2856US2024153864A1Metallization levels with skip via and dielectric layerIBM·Filed 2022·Application pending·0 cites
- 2956US2024153865A1Metal via multi-levelsIBM·Filed 2022·Application pending·0 cites
- 3055US2024162087A1Mandrel-pull-first interconnect patterningIBM·Filed 2022·Application pending·0 cites
- 3155US2024038547A1Method and structure to form connector tabs in subtractive patterningIBM·Filed 2022·Application pending·0 cites
- 3255US2024071904A1Skip via with localized spacerIBM·Filed 2022·Application pending·0 cites
- 3354US10062605B2Via and chamfer control for advanced interconnectsIBM·Filed 2017·Granted Aug 28, 2018·0 cites·8 claims
- 3454US2024188447A1Memory structure with non-ion beam etched mtj and top electrodeIBM·Filed 2022·Application pending·0 cites
- 3553US2024419882A1Selective cuts to remove predicted interconnect bulging regionsIBM·Filed 2023·Application pending·0 cites
- 3651US9972533B2Aligning conductive vias with trenchesIBM·Filed 2017·Granted May 15, 2018·0 cites·20 claims
- 3751US2023170293A1Beol top via wirings with dual damascene via and super via redundancyIBM·Filed 2021·Application pending·0 cites
- 3851US2018204724A1Image transfer using euv lithographic structure and double patterning processIBM·Filed 2017·Application pending·0 cites
- 3947US11600519B2Skip-via proximity interconnectIBM·Filed 2019·Granted Mar 7, 2023·0 cites·19 claims
- 4045US2015001735A1Multipatterning via shrink method using ald spacerST MICROELECTRONICS INC·Filed 2014·Application pending·0 cites
- 4144US11075161B2Large via bufferIBM·Filed 2019·Granted Jul 27, 2021·0 cites·10 claims
- 4242US2020185269A1Self-aligned litho-etch double patterningIBM·Filed 2018·Application pending·0 cites
- 4341US2020066520A1Alternating hard mask for tight-pitch fin formationIBM·Filed 2018·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →