Inventor · disambiguated record
Yaron Schiller
Also filed as: SCHILLER YARON
4 granted patents·4 citations·filing 2018–2020
60Inventor score
Technology areasG06F
Files withCADENCE DESIGN SYSTEMS INC4
Top patents by PatentIndex Score
4 records- 0170US10853546B1Method and system for sequential equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Dec 1, 2020·2 cites·19 claims
- 0270US10782767B1System, method, and computer program product for clock gating in a formal verificationCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 22, 2020·2 cites·17 claims
- 0347US11080448B1Method and system for formal bug huntingCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Aug 3, 2021·0 cites·14 claims
- 0442US11151295B1Method and system for sequential equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Oct 19, 2021·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →