Inventor · disambiguated record
Yanjuan Zhan
Also filed as: ZHAN YANJUAN
7 granted patents·66 citations·filing 2016–2018
85Inventor score
Files withCADENCE DESIGN SYSTEMS INC7
Top patents by PatentIndex Score
7 records- 0192US10409357B1Command-oriented low power control method of high-bandwidth-memory systemCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 10, 2019·14 cites·20 claims
- 0291US10162522B1Architecture of single channel memory controller to support high bandwidth memory of pseudo channel mode or legacy modeCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Dec 25, 2018·12 cites·20 claims
- 0390US10067689B1Method and apparatus for high bandwidth memory read and write data path trainingCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 4, 2018·10 cites·20 claims
- 0488US10297311B1Systems and methods for memory protocol trainingCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted May 21, 2019·9 cites·20 claims
- 0585US10852956B1Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reorderingCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Dec 1, 2020·5 cites·20 claims
- 0685US10203875B1Methods and systems for implementing high bandwidth memory command address bus trainingCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Feb 12, 2019·9 cites·12 claims
- 0783US9881664B1Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM deviceCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jan 30, 2018·7 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →