Inventor · disambiguated record
Yei-Hsiung Lin
Also filed as: LIN YEI-HSIUNG
5 granted patents·5 pending applications·24 citations·filing 1998–2004
75Inventor score
Top patents by PatentIndex Score
10 records- 0141US6225209B1Method of fabricating crack resistant inter-layer dielectric for a salicide processUNITED MICROELECTRONICS CORP·Filed 1998·Granted May 1, 2001·10 cites·6 claims
- 0237US6114196AMethod of fabricating metal-oxide semiconductor transistorUNITED MICROELECTRONICS CORP·Filed 1999·Granted Sep 5, 2000·5 cites·8 claims
- 0334US7432181B2Method of forming self-aligned silicidesTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 7, 2008·0 cites·17 claims
- 0434US6376359B1Method of manufacturing metallic interconnectUNITED MICROELECTRONICS CORP·Filed 1998·Granted Apr 23, 2002·6 cites·13 claims
- 0533US2003038371A1Method of forming a metallic interconnect structure with a metallic spacerFiled 2001·Application pending·0 cites
- 0633US2002177299A1Interconnects with dielectric spacers and method for forming the sameFiled 2001·Application pending·0 cites
- 0733US2002177080A1Interconnects with dual dielectric spacers and method for forming the sameFiled 2001·Application pending·0 cites
- 0833US2002115001A1Electrostatic discharge effect free maskFiled 2001·Application pending·0 cites
- 0932US2002102785A1Method for forming shallow junctions by increasing width of photoresist and using implanting through poly filmFiled 2001·Application pending·0 cites
- 1031US6242315B1Method of manufacturing mixed mode semiconductor deviceUNITED MICROELECTRONICS CORP·Filed 1998·Granted Jun 5, 2001·3 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →