Inventor · disambiguated record
Ying Li
Also filed as: LI YING · LI YING-MENG
10 granted patents·254 citations·filing 1994–2021
90Inventor score
Files withCADENCE DESIGN SYSTEMS INC5VLSI TECHNOLOGY INC2AMAZON TECH INC1CANDACE DESIGN SYSTEMS INC1VSLI TECHNOLOGY INC1
Top patents by PatentIndex Score
10 records- 0192US10409357B1Command-oriented low power control method of high-bandwidth-memory systemCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 10, 2019·14 cites·20 claims
- 0291US10162522B1Architecture of single channel memory controller to support high bandwidth memory of pseudo channel mode or legacy modeCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Dec 25, 2018·12 cites·20 claims
- 0386US10579303B1Memory controller having command queue with entries mergingCANDACE DESIGN SYSTEMS INC·Filed 2016·Granted Mar 3, 2020·11 cites·20 claims
- 0485US10852956B1Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reorderingCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Dec 1, 2020·5 cites·20 claims
- 0583US9881664B1Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM deviceCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jan 30, 2018·7 cites·20 claims
- 0682US11790049B1Techniques for improving machine-learning accuracy and convergenceAMAZON TECH INC·Filed 2021·Granted Oct 17, 2023·3 cites·20 claims
- 0775US5974245AMethod and apparatus for making integrated circuits by inserting buffers into a netlistVSLI TECHNOLOGY INC·Filed 1997·Granted Oct 26, 1999·69 cites·20 claims
- 0875US5638291AMethod and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skewVLSI TECHNOLOGY INC·Filed 1994·Granted Jun 10, 1997·63 cites·20 claims
- 0972US5666290AInteractive time-driven method of component placement that more directly constrains critical paths using net-based constraintsVLSI TECHNOLOGY INC·Filed 1995·Granted Sep 9, 1997·69 cites·22 claims
- 1053US7716621B1Method and system for improving signal integrity in integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted May 11, 2010·1 cites·42 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →