Inventor · disambiguated record
Yung-Chin Hou
Also filed as: HOU YUNG-CHIN
33 granted patents·11 pending applications·257 citations·filing 2005–2025
97Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD19TAIWAN SEMICONDUCTOR MFG13HOU YUNG-CHIN6CHEN KUN-LUNG1KESHAVARZI ALI1
Top patents by PatentIndex Score
44 records- 0197US11113443B1Integrated circuit with thicker metal lines on lower metallization layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 7, 2021·6 cites·20 claims
- 0296US10678973B2Machine-learning design enablement platformTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jun 9, 2020·13 cites·20 claims
- 0395US8507957B2Integrated circuit layouts with power rails under bottom metal layerHOU YUNG-CHIN·Filed 2011·Granted Aug 13, 2013·30 cites·18 claims
- 0493US8255837B2Methods for cell boundary isolation in double patterning designLU LEE-CHUNG·Filed 2009·Granted Aug 28, 2012·19 cites·20 claims
- 0593US7808051B2Standard cell without OD space effect in Y-directionTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Oct 5, 2010·29 cites·21 claims
- 0692US8504972B2Standard cells having flexible layout architecture/boundariesHOU YUNG-CHIN·Filed 2010·Granted Aug 6, 2013·21 cites·19 claims
- 0792US7821039B2Layout architecture for improving circuit performanceTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Oct 26, 2010·30 cites·29 claims
- 0889US11017149B2Machine-learning design enablement platformTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted May 25, 2021·2 cites·20 claims
- 0988US8001494B2Table-based DFM for accurate post-layout analysisTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Aug 16, 2011·16 cites·20 claims
- 1086US11593546B2Integrated circuit with thicker metal lines on lower metallization layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 28, 2023·1 cites·20 claims
- 1186US8631366B2Integrated circuit design using DFM-enhanced architectureHOU YUNG-CHIN·Filed 2010·Granted Jan 14, 2014·10 cites·33 claims
- 1286US7932566B2Structure and system of mixing poly pitch cell design under default poly pitch design rulesTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Apr 26, 2011·15 cites·20 claims
- 1386US7458051B2ECO cell for reducing leakage powerTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Nov 25, 2008·14 cites·12 claims
- 1485US8217469B2Contact implement structure for high density designHOU YUNG-CHIN·Filed 2010·Granted Jul 10, 2012·17 cites·20 claims
- 1581US8431985B2Layout and process of forming contact plugsHOU YUNG-CHIN·Filed 2010·Granted Apr 30, 2013·6 cites·12 claims
- 1680US2025357435A1Integrated circuit device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 1779US12094880B2Integrated circuits and manufacturing methods thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 1876US12008302B2Integrated circuit with thicker metal lines on lower metallization layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 11, 2024·0 cites·20 claims
- 1976US2025324665A1Transistor contacts and methods of forming thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2072US7350177B2Configurable logic and memory devicesTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Mar 25, 2008·6 cites·15 claims
- 2172US2023275081A1Semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 2269US7467365B2Sanity checker for integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Dec 16, 2008·5 cites·15 claims
- 2369US2024274585A1Integrated circuit device and method of manufacturingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 2469US2024304685A1Transistor contacts and methods of forming thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 2568US8504965B2Method for non-shrinkable IP integrationLIU HUNG-YI·Filed 2010·Granted Aug 6, 2013·3 cites·20 claims
- 2665US11682665B2Semiconductor layout with different row heightsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 20, 2023·0 cites·20 claims
- 2765US8671382B2Method of generating RC technology fileTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Mar 11, 2014·1 cites·20 claims
- 2864US11581314B2Integrated circuits and manufacturing methods thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Feb 14, 2023·0 cites·19 claims
- 2964US8671367B2Integrated circuit design in optical shrink technology nodeWANG CHUNG-HSING·Filed 2008·Granted Mar 11, 2014·3 cites·16 claims
- 3063US8201111B2Table-based DFM for accurate post-layout analysisHOU YUNG-CHIN·Filed 2011·Granted Jun 12, 2012·1 cites·20 claims
- 3162US7797668B2Method for optimally converting a circuit design into a semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Sep 14, 2010·2 cites·13 claims
- 3262US7401302B2System on chip development with reconfigurable multi-project wafer technologyTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jul 15, 2008·2 cites·5 claims
- 3361US2025293082A1Method and system of arranging patterns of semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 3458US7913141B2Power gating in integrated circuits for leakage reductionTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Mar 22, 2011·4 cites·6 claims
- 3557US8261219B2System on chip development with reconfigurable multi-project wafer technologyCHEN KUN-LUNG·Filed 2008·Granted Sep 4, 2012·1 cites·10 claims
- 3657US2024355707A1Power rail arrangements in integrated circuits having stacked transistorsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 3756US2024303407A1Power distribution structure, manufacturing method, and layout methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 3855US2024355821A1Semiconductor device and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 3954US10535655B2Integrated circuits and manufacturing methods thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jan 14, 2020·0 cites·14 claims
- 4049US8418112B2Method of generating RC technology fileSU KE-YING·Filed 2011·Granted Apr 9, 2013·0 cites·22 claims
- 4148US9312260B2Integrated circuits and manufacturing methods thereofKESHAVARZI ALI·Filed 2011·Granted Apr 12, 2016·0 cites·20 claims
- 4245US9811627B2Method of component partitions on system on chip and device thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Nov 7, 2017·0 cites·20 claims
- 4344US2010127333A1novel layout architecture for performance enhancementTAIWAN SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 4438US2007152745A1System and method for reducing leakage current of an integrated circuitTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →