Inventor · disambiguated record
Yu-Hua Lee
Also filed as: LEE YU-HUA
44 granted patents·2 pending applications·1,208 citations·filing 1994–2006
98Inventor score
Files withTAIWAN SEMICONDUCTOR MFG42IND TECH RES INST2TAIWAN SEMICONDUCTOR FOR MFG C1YANG CHIN-TIEN1
Top patents by PatentIndex Score
46 records- 0191US6042999ARobust dual damascene processTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Mar 28, 2000·120 cites·41 claims
- 0286US6162686AMethod for forming a fuse in integrated circuit applicationTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 19, 2000·87 cites·12 claims
- 0385US6436763B1Process for making embedded DRAM circuits having capacitor under bit-line (CUB)TAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Aug 20, 2002·39 cites·20 claims
- 0485US6037213AMethod for making cylinder-shaped capacitors for dynamic random access memoryTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Mar 14, 2000·55 cites·20 claims
- 0585US5597754AIncreased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal processIND TECH RES INST·Filed 1995·Granted Jan 28, 1997·88 cites·20 claims
- 0684US5985765AMethod for reducing bonding pad loss using a capping layer when etching bonding pad passivation openingsTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Nov 16, 1999·78 cites·20 claims
- 0783US6307213B1Method for making a fuse structure for improved repaired yields on semiconductor memory devicesTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Oct 23, 2001·31 cites·5 claims
- 0882US6165839AProcess to fabricate a cylindrical, capacitor structure under a bit line structure for a dynamic random access memory cellTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 26, 2000·53 cites·13 claims
- 0977US6100116AMethod to form a protected metal fuseTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Aug 8, 2000·51 cites·9 claims
- 1074US6121073AMethod for making a fuse structure for improved repaired yields on semiconductor memory devicesTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Sep 19, 2000·40 cites·23 claims
- 1172US6323118B1Borderless dual damascene contactTAIWAN SEMICONDUCTOR FOR MFG C·Filed 1998·Granted Nov 27, 2001·48 cites·23 claims
- 1270US6228736B1Modified method for forming cylinder-shaped capacitors for dynamic random access memory (DRAM)TAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted May 8, 2001·31 cites·11 claims
- 1369US6077738AInter-level dielectric planarization approach for a DRAM crown capacitor processTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 20, 2000·41 cites·26 claims
- 1469US6033981AKeyhole-free process for high aspect ratio gap filingTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Mar 7, 2000·36 cites·25 claims
- 1568US6403416B1Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM)TAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 11, 2002·29 cites·22 claims
- 1668US5429979AMethod of forming a dram cell having a ring-type stacked capacitorIND TECH RES INST·Filed 1994·Granted Jul 4, 1995·27 cites·22 claims
- 1767US6265315B1Method for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jul 24, 2001·34 cites·28 claims
- 1867US6015734AMethod for improving the yield on dynamic random access memory (DRAM) with cylindrical capacitor structuresTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 18, 2000·23 cites·20 claims
- 1961US6015733AProcess to form a crown capacitor structure for a dynamic random access memory cellTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 18, 2000·27 cites·22 claims
- 2060US6274426B1Self-aligned contact process for a crown shaped dynamic random access memory capacitor structureTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 14, 2001·25 cites·9 claims
- 2160US6194234B1Method to evaluate hemisperical grain (HSG) polysilicon surfaceTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Feb 27, 2001·23 cites·12 claims
- 2260US5854119ARobust method of forming a cylinder capacitor for DRAM circuitsTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 29, 1998·24 cites·20 claims
- 2358US7015129B2Bond pad scheme for Cu processTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Mar 21, 2006·7 cites·20 claims
- 2458US6187659B1Node process integration technology to improve data retention for logic based embedded dramTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Feb 13, 2001·17 cites·17 claims
- 2558US6136695AMethod for fabricating a self-aligned contactTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Oct 24, 2000·23 cites·14 claims
- 2657US6103455AMethod to form a recess free deep contactTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Aug 15, 2000·22 cites·15 claims
- 2757US6020236AMethod to form capacitance node contacts with improved isolation in a DRAM processTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Feb 1, 2000·15 cites·20 claims
- 2856US7160811B2Laminated silicate glass layer etch stop method for fabricating microelectronic productTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Jan 9, 2007·5 cites·19 claims
- 2954US5989784AEtch recipe for embedded DRAM passivation with etch stopping layer schemeTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Nov 23, 1999·19 cites·24 claims
- 3049US6844626B2Bond pad scheme for Cu processTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jan 18, 2005·3 cites·13 claims
- 3149US6013550AMethod to define a crown shaped storage node structure, and an underlying conductive plug structure, for a dynamic random access memory cellTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 11, 2000·15 cites·26 claims
- 3248US6586162B2Simple photo development step to form TiSix gate in DRAM processTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Jul 1, 2003·3 cites·21 claims
- 3347US6600228B2Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal ruleTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jul 29, 2003·2 cites·6 claims
- 3447US6555435B2Method to eliminate shorts between adjacent contacts due to interlevel dielectric voidsTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Apr 29, 2003·2 cites·2 claims
- 3545US7056821B2Method for manufacturing dual damascene structure with a trench formed firstTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jun 6, 2006·3 cites·14 claims
- 3645US6107155AMethod for making a more reliable storage capacitor for dynamic random access memory (DRAM)TAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Aug 22, 2000·8 cites·18 claims
- 3745US6017824APassivation etching procedure, using a polysilicon stop layer, for repairing embedded DRAM cellsTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 25, 2000·12 cites·23 claims
- 3844US6956254B2Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturingTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Oct 18, 2005·3 cites·24 claims
- 3944US6103630AAdding SF6 gas to improve metal undercut for hardmask metal etchingTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Aug 15, 2000·11 cites·17 claims
- 4043US6294456B1Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal ruleTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Sep 25, 2001·9 cites·9 claims
- 4142US5989954AMethod for forming a cylinder capacitor in the dram processTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Nov 23, 1999·6 cites·34 claims
- 4240US6235580B1Process for forming a crown shaped capacitor structure for a DRAM deviceTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted May 22, 2001·6 cites·18 claims
- 4336US6365464B1Method to eliminate shorts between adjacent contacts due to interlevel dielectric voidsTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Apr 2, 2002·5 cites·20 claims
- 4436US2006194426A1Method for manufacturing dual damascene structure with a trench formed firstYANG CHIN-TIEN·Filed 2006·Application pending·0 cites
- 4534US2005173799A1Interconnect structure and method for its fabricatingTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 4629US7482278B1Key-hole free process for high aspect ratio gap filling with reentrant spacerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jan 27, 2009·2 cites·24 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →