Method for manufacturing dual damascene structure with a trench formed first

Abstract

A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.

1 . A method of manufacturing a dual damascene structure with a trench formed first, comprising the steps of: 
 forming a dielectric layer on a substrate;    patterning the dielectric layer to form a trench on an upper part of the dielectric layer;    filling with a sacrificial layer into the trench;    patterning the sacrificial layer and the dielectric layer to form a via on a lower part of the dielectric layer;    removing the sacrificial layer;    filling with a metal layer; and    planarizing the metal layer.    
   
   
       2 . The method of  claim 1 , wherein the dielectric layer further comprises a first etching stop layer below the dielectric layer, and a second etching stop layer above the dielectric layer.  
   
   
       3 . The method of  claim 2 , wherein the step of patterning the dielectric layer to form the trench on the upper part of the dielectric layer, further comprising: 
 forming a first patterned photoresist layer on the second etching stop layer; and    etching through the second etching stop layer and stopping in the dielectric layer.    
   
   
       4 . The method of  claim 2 , wherein the step of patterning the sacrificial layer and the dielectric layer to form the via on the lower part of the dielectric layer is terminated at the first etching stop layer.  
   
   
       5 . The method of  claim 2 , wherein the first etching stop layer comprises a diffusion-barrier layer.  
   
   
       6 . The method of  claim 2 , wherein the second etching stop layer comprises a hard mask layer.  
   
   
       7 . The method of  claim 2 , wherein the second etching stop layer comprises an anti-reflection layer.  
   
   
       8 . The method of  claim 1 , further comprising a step of planarizing the sacrificial layer prior to the step of patterning the sacrificial layer and the dielectric layer to form the via on the lower part of the dielectric layer.  
   
   
       9 . The method of  claim 1 , wherein the metal layer comprises copper.  
   
   
       10 . The method of  claim 1 , wherein the dielectric layer is made of a material selected from a group consisting of fluorinated silicate glass (FSG), silicon dioxide, black diamond (BD), SiLK, CORAL, methyl silsesquioxane (MSQ), and hydrogen silsesquioxane (HSQ).  
   
   
       11 . The method of  claim 1 , wherein the dielectric layer has a dielectric constant of about 1.0 to about 4.0.  
   
   
       12 . The method of  claim 1 , wherein a depth of the trench is less than a thickness of the dielectric layer.  
   
   
       13 . The method of  claim 1 , wherein the sacrificial layer is 0.5-1.5 times a thickness of the dielectric layer.  
   
   
       14 . The method of  claim 1 , wherein an etching rate ratio of the sacrificial layer to the dielectric layer is about 0.7:1 to 1.3:1.  
   
   
       15 . A dual damascene process, comprising the steps of: 
 forming a dielectric layer on a substrate, wherein an upper portion of the dielectric layer comprises a sacrificial layer;    removing a partial portion of the sacrificial layer and a partial portion of the dielectric layer, wherein the partial portion of the dielectric layer is directly under the partial portion of the sacrificial layer;    removing the sacrificial layer to form a dual damascene structure; and    filling with a metal layer.    
   
   
       16 . The dual damascene process of  claim 15 , wherein the dielectric layer further comprises a first etching stop layer below the dielectric layer, and a second etching stop layer above the dielectric layer.  
   
   
       17 . The dual damascene process of  claim 16 , wherein the step of removing a partial portion of the sacrificial layer and a partial portion of the dielectric layer is terminated at the first etching stop layer.  
   
   
       18 . The dual damascene process of  claim 16 , wherein the first etching stop layer comprises a diffusion-barrier layer.  
   
   
       19 . The dual damascene process of  claim 16 , wherein the second etching stop layer comprises a hard mask layer, or an anti-reflection layer.  
   
   
       20 . The dual damascene process of  claim 15 , wherein the metal layer comprises copper.  
   
   
       21 . The dual damascene process of  claim 15 , wherein the dielectric layer is made of a material selected from a group consisting of fluorinated silicate glass (FSG), silicon dioxide, black diamond (BD), SiLK, CORAL, methyl silsesquioxane (MSQ), and hydrogen silsesquioxane (HSQ).  
   
   
       22 . The dual damascene process of  claim 15 , wherein the dielectric layer has a dielectric constant of about 1.0 to about 4.0.  
   
   
       23 . The dual damascene process of  claim 15 , wherein a depth of the trench is less than a thickness of the dielectric layer.  
   
   
       24 . The dual damascene process of  claim 15 , wherein the sacrificial layer is 0.5-1.5 times a thickness of the dielectric layer.  
   
   
       25 . The dual damascene process of  claim 15 , wherein an etching rate ratio of the sacrificial layer to the dielectric layer is about 0.7:1 to 1.3:1.