Inventor · disambiguated record
Yung-Hsu Wu
Also filed as: WU YUNG-HSU
54 granted patents·10 pending applications·205 citations·filing 2011–2025
98Inventor score
Top patents by PatentIndex Score
64 records- 0197US9773676B2Lithography using high selectivity spacers for pitch reductionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Sep 26, 2017·17 cites·19 claims
- 0297US9659864B2Method and apparatus for forming self-aligned via with selectively deposited etching stop layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted May 23, 2017·24 cites·20 claims
- 0397US9177797B2Lithography using high selectivity spacers for pitch reductionTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 3, 2015·28 cites·20 claims
- 0497US9123776B2Self-aligned double spacer patterning processTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 1, 2015·26 cites·20 claims
- 0596US9418868B1Method of fabricating semiconductor device with reduced trench distortionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 16, 2016·11 cites·20 claims
- 0694US10014175B2Lithography using high selectivity spacers for pitch reductionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jul 3, 2018·7 cites·20 claims
- 0794US9627206B2Method of double patterning lithography process using plurality of mandrels for integrated circuit applicationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Apr 18, 2017·9 cites·20 claims
- 0894US9431297B2Method of forming an interconnect structure for a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Aug 30, 2016·15 cites·20 claims
- 0993US9922927B2Method and apparatus for forming self-aligned via with selectively deposited etching stop layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Mar 20, 2018·6 cites·20 claims
- 1093US9911646B2Self-aligned double spacer patterning processTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Mar 6, 2018·6 cites·20 claims
- 1191US10170306B2Method of double patterning lithography process using plurality of mandrels for integrated circuit applicationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jan 1, 2019·5 cites·20 claims
- 1290US9490136B1Method of forming trench cutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Nov 8, 2016·8 cites·20 claims
- 1387US12394633B2Method of fabricating semiconductor device with reduced trench distortionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Aug 19, 2025·0 cites·20 claims
- 1487US10163654B2Method of fabricating semiconductor device with reduced trench distortionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 25, 2018·3 cites·8 claims
- 1587US9129906B2Self-aligned double spacer patterning processTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 8, 2015·6 cites·20 claims
- 1684US9997404B2Method of forming an interconnect structure for a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jun 12, 2018·3 cites·20 claims
- 1782US8889544B2Dielectric protection layer as a chemical-mechanical polishing stop layerWU YUNG-HSU·Filed 2011·Granted Nov 18, 2014·8 cites·20 claims
- 1881US9947535B2Trench formation using horn shaped spacerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Apr 17, 2018·2 cites·20 claims
- 1980US10534273B2Multi-metal fill with self-aligned patterning and dielectric with voidsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jan 14, 2020·2 cites·20 claims
- 2080US9136162B2Trench formation using horn shaped spacerTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 15, 2015·3 cites·20 claims
- 2180US2024085803A1Multi-metal fill with self-aligned patterning and dielectric with voidsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 2279US11894238B2Method of fabricating semiconductor device with reduced trench distortionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Feb 6, 2024·0 cites·20 claims
- 2379US10714421B2Structure and formation method of semiconductor device with self-aligned conductive featuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jul 14, 2020·2 cites·20 claims
- 2479US9831117B2Self-aligned double spacer patterning processTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Nov 28, 2017·2 cites·20 claims
- 2578US11860550B2Multi-metal fill with self-aligned patterning and dielectric with voidsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jan 2, 2024·0 cites·20 claims
- 2678US2024321573A1Using A Self-Assembly Layer To Facilitate Selective Formation of An Etching Stop LayerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2778US2025336806A1Semiconductor device structure and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2878US2024339406A1Integrated circuit interconnect structures with air gapsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2977US10867913B2Method and apparatus for forming self-aligned via with selectively deposited etching stop layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 15, 2020·1 cites·20 claims
- 3076US12300600B2Semiconductor device with self-aligned conductive featuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted May 13, 2025·0 cites·20 claims
- 3176US11848190B2Barrier-less structuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Dec 19, 2023·0 cites·19 claims
- 3276US9576896B2Semiconductor arrangement and formation thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Feb 21, 2017·2 cites·20 claims
- 3375US9412649B1Method of fabricating semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 9, 2016·2 cites·20 claims
- 3475US9209076B2Method of double patterning lithography process using plurality of mandrels for integrated circuit applicationsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 8, 2015·2 cites·20 claims
- 3574US12412831B2Semiconductor device structure and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Sep 9, 2025·0 cites·20 claims
- 3674US12062611B2Integrated circuit interconnect structures with air gapsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 13, 2024·0 cites·19 claims
- 3774US11532552B2Method and apparatus for forming self-aligned via with selectively deposited etching stop layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Dec 20, 2022·0 cites·20 claims
- 3873US12080593B2Barrier-less structuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Sep 3, 2024·0 cites·20 claims
- 3973US11387113B2Method of fabricating semiconductor device with reduced trench distortionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jul 12, 2022·0 cites·20 claims
- 4072US12009202B2Using a self-assembly layer to facilitate selective formation of an etching stop layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jun 11, 2024·0 cites·20 claims
- 4172US10269634B2Semiconductor device having voids and method of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Apr 23, 2019·2 cites·18 claims
- 4271US9330989B2System and method for chemical-mechanical planarization of a metal layerTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted May 3, 2016·2 cites·20 claims
- 4370US11011421B2Semiconductor device having voids and method of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted May 18, 2021·0 cites·20 claims
- 4470US9093386B2Spacer-damage-free etchingTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jul 28, 2015·1 cites·20 claims
- 4569US11404367B2Method for forming semiconductor device with self-aligned conductive featuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Aug 2, 2022·0 cites·20 claims
- 4666US10916443B2Spacer-damage-free etchingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Feb 9, 2021·0 cites·20 claims
- 4765US11422475B2Multi-metal fill with self-aligned patterning and dielectric with voidsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Aug 23, 2022·0 cites·20 claims
- 4864US10818509B2Method of fabricating semiconductor device with reduced trench distortionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Oct 27, 2020·0 cites·20 claims
- 4960US11244898B2Integrated circuit interconnect structures with air gapsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Feb 8, 2022·0 cites·20 claims
- 5060US10784160B2Semiconductor device having voids and method of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Sep 22, 2020·0 cites·20 claims
Showing the top 50 of 64 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →