Inventor · disambiguated record
Zhuo Li
Also filed as: LI ZHUO · LI ZHUO D
123 granted patents·5 pending applications·650 citations·filing 2004–2022
99Inventor score
Files withCADENCE DESIGN SYSTEMS INC67IBM38ALPERT CHARLES J10ALPERT CHARLES JAY10AGARWAL KANAK BEHARI1
Top patents by PatentIndex Score
128 records- 0196US11645441B1Machine-learning based clustering for clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted May 9, 2023·12 cites·20 claims
- 0296US10963617B1Modifying route topology to fix clock tree violationsCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 30, 2021·11 cites·20 claims
- 0395US11734485B1Routing congestion based on fractional via cost and via densityCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Aug 22, 2023·7 cites·20 claims
- 0494US11620428B1Post-CTS clock tree restructuringCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Apr 4, 2023·5 cites·20 claims
- 0594US11354479B1Post-CTS clock tree restructuring with ripple moveCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Jun 7, 2022·5 cites·20 claims
- 0694US8635577B2Timing refinement re-routingKAZDA MICHAEL ANTHONY·Filed 2012·Granted Jan 21, 2014·87 cites·17 claims
- 0793US11520959B1Pruning of buffering candidates for improved efficiency of evaluationCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Dec 6, 2022·5 cites·20 claims
- 0893US11244099B1Machine-learning based prediction method for iterative clustering during clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Feb 8, 2022·4 cites·18 claims
- 0993US10963618B1Multi-dimension clock gate design in clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 30, 2021·5 cites·20 claims
- 1093US10963620B1Buffer insertion technique to consider edge spacing and stack via design rulesCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 30, 2021·4 cites·20 claims
- 1193US10740532B1Route driven placement of fan-out clock driversCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Aug 11, 2020·6 cites·20 claims
- 1293US8677299B1Latch clustering with proximity to local clock buffersIBM·Filed 2013·Granted Mar 18, 2014·22 cites·17 claims
- 1392US11188702B1Dynamic weighting scheme for local cluster refinementCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Nov 30, 2021·3 cites·20 claims
- 1492US10755024B1System and method for routing in an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Aug 25, 2020·13 cites·17 claims
- 1592US8954912B2Structured placement of latches/flip-flops to minimize clock power in high-performance designsIBM·Filed 2012·Granted Feb 10, 2015·18 cites·25 claims
- 1692US8495548B2Multi-patterning lithography aware cell placement in integrated circuit designAGARWAL KANAK BEHARI·Filed 2011·Granted Jul 23, 2013·22 cites·20 claims
- 1791US10460066B1Routing framework to resolve single-entry constraint violations for integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·9 cites·20 claims
- 1891US8793636B2Placement of structured netsALPERT CHARLES J·Filed 2011·Granted Jul 29, 2014·17 cites·23 claims
- 1990US10997352B1Routing congestion based on layer-assigned net and placement blockageCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted May 4, 2021·9 cites·11 claims
- 2090US10885250B1Clock gate placement with data path awarenessCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Jan 5, 2021·3 cites·20 claims
- 2190US10860764B1Layer assignment technique to improve timing in integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Dec 8, 2020·8 cites·20 claims
- 2289US11321514B1Macro clock latency computation in multiple iteration clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted May 3, 2022·4 cites·20 claims
- 2389US11132489B1Layer assignment based on wirelength thresholdCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Sep 28, 2021·3 cites·20 claims
- 2489US10282506B1Systems and methods for clock tree clusteringCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 7, 2019·6 cites·20 claims
- 2588US11797747B1Identifying redundant logic based on clock gate enable conditionCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Oct 24, 2023·3 cites·20 claims
- 2688US10885257B1Routing congestion based on via spacing and pin densityCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jan 5, 2021·6 cites·14 claims
- 2788US10643019B1View pruning for routing tree optimizationCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted May 5, 2020·6 cites·20 claims
- 2888US10216880B1Systems and methods for power efficient flop clusteringCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Feb 26, 2019·6 cites·20 claims
- 2988US8782584B2Post-placement cell shiftingIBM·Filed 2013·Granted Jul 15, 2014·10 cites·1 claims
- 3088US7299442B2Probabilistic congestion prediction with partial blockagesIBM·Filed 2005·Granted Nov 20, 2007·19 cites·18 claims
- 3187US10643014B1Irregular sink arrangement for balanced routing tree structuresCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted May 5, 2020·5 cites·20 claims
- 3287US8365120B2Resolving global coupling timing and slew violations for buffer-dominated designsIBM·Filed 2010·Granted Jan 29, 2013·11 cites·21 claims
- 3386US10614261B1Honoring pin insertion delay during clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Apr 7, 2020·5 cites·20 claims
- 3486US10102328B1System and method for constructing spanning treesCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 16, 2018·5 cites·17 claims
- 3586US8881089B1Physical synthesis optimization with fast metric checkIBM·Filed 2013·Granted Nov 4, 2014·11 cites·14 claims
- 3686US8667441B2Clock optimization with local clock buffer control optimizationALPERT CHARLES J·Filed 2010·Granted Mar 4, 2014·10 cites·20 claims
- 3785US8418113B1Consideration of local routing and pin access during VLSI global routingALPERT CHARLES J·Filed 2011·Granted Apr 9, 2013·9 cites·24 claims
- 3884US10860757B1Multicorner skew scheduling circuit designCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Dec 8, 2020·4 cites·20 claims
- 3984US10509878B1Systems and methods for routing track assignmentCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Dec 17, 2019·4 cites·20 claims
- 4084US10460064B1Partition-aware grid graph based hierarchical global routingCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·4 cites·20 claims
- 4184US10354183B2Power-driven synthesis under latency constraintsIBM·Filed 2014·Granted Jul 16, 2019·5 cites·18 claims
- 4284US10031994B1Systems and methods for congestion and routability aware detailed placementCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jul 24, 2018·5 cites·18 claims
- 4383US10769345B1Clock tree optimization by moving instances toward core routeCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 8, 2020·4 cites·20 claims
- 4483US10706202B1Devices and methods for balanced routing tree structuresCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jul 7, 2020·3 cites·20 claims
- 4583US10289795B1Routing tree topology generationCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·4 cites·20 claims
- 4683US10095824B1Systems and methods for symmetric H-tree construction with complicated routing blockagesCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 9, 2018·4 cites·20 claims
- 4783US9092591B2Automatic generation of wire tag lists for a metal stackIBM·Filed 2014·Granted Jul 28, 2015·6 cites·19 claims
- 4883US8589848B2Datapath placement using tiered assignmentALPERT CHARLES J·Filed 2012·Granted Nov 19, 2013·7 cites·25 claims
- 4983US7707530B2Incremental timing-driven, physical-synthesis using discrete optimizationIBM·Filed 2007·Granted Apr 27, 2010·13 cites·15 claims
- 5082US10860775B1Clock pin to clock tap assignment based on circuit device connectivityCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Dec 8, 2020·3 cites·20 claims
Showing the top 50 of 128 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →