Inventor · disambiguated record
Zsolt Tokei
Also filed as: TOKEI ZSOLT · TÖKEI ZSOLT
11 granted patents·7 pending applications·6 citations·filing 2007–2025
80Inventor score
Top patents by PatentIndex Score
18 records- 0178US9859161B2Self-aligned interconnectsIMEC VZW·Filed 2017·Granted Jan 2, 2018·3 cites·16 claims
- 0275US11005016B2Apex angle reduction in a LED device with a LED arrayIMEC VZW·Filed 2019·Granted May 11, 2021·2 cites·18 claims
- 0360US2025185520A1Josephson Junction Device and Method of Producing the DeviceIMEC VZW·Filed 2024·Application pending·0 cites
- 0458US2024234207A9Method for interconnecting a buried wiring line and a source/drain bodyIMEC VZW·Filed 2023·Application pending·0 cites
- 0557US2025029872A1Method for producing an interconnect viaIMEC VZW·Filed 2024·Application pending·0 cites
- 0656US9553586B2Filed programmable gate array device with programmable interconnect in back end of line portion of the deviceIMEC VZW·Filed 2014·Granted Jan 24, 2017·1 cites·8 claims
- 0753US12431389B2Superconductive interconnect structureIMEC VZW·Filed 2022·Granted Sep 30, 2025·0 cites·15 claims
- 0853US2024170328A1Method for Forming an Interconnection StructureIMEC VZW·Filed 2023·Application pending·0 cites
- 0950US12438038B2Forming vias in a semiconductor deviceTOKYO ELECTRON LTD·Filed 2021·Granted Oct 7, 2025·0 cites·20 claims
- 1050US11342261B2Integrated circuit with an interconnection system having a multilevel layer providing multilevel routing tracks and method of manufacturing the sameIMEC VZW·Filed 2019·Granted May 24, 2022·0 cites·17 claims
- 1150US2025300006A1Split conductive via fabricationIMEC VZW·Filed 2025·Application pending·0 cites
- 1248US11270912B2Method for forming a via hole self-aligned with a metal block on a substrateIMEC VZW·Filed 2020·Granted Mar 8, 2022·0 cites·11 claims
- 1347US11088070B2Method of forming a multi-level interconnect structure in a semiconductor deviceIMEC VZW·Filed 2020·Granted Aug 10, 2021·0 cites·14 claims
- 1446US2010207177A1Method for producing a copper contactIMEC·Filed 2009·Application pending·0 cites
- 1543US11264271B2Semiconductor fabrication method for producing nano-scaled electrically conductive linesIMEC VZW·Filed 2020·Granted Mar 1, 2022·0 cites·10 claims
- 1641US9997458B2Method for manufacturing germamde interconnect structures and corresponding interconnect structuresIMEC VZW·Filed 2013·Granted Jun 12, 2018·0 cites·22 claims
- 1740US10395978B2Method of patterning target layerIMEC VZW·Filed 2018·Granted Aug 27, 2019·0 cites·18 claims
- 1840US2008254605A1Method of reducing the interfacial oxide thicknessIMEC INTER UNI MICRO ELECTR·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →