Inventor · name-matched record
LIN CHUNG-HSUN
3 granted patents·18 pending applications·0 citations·filing 2020–2024
39Inventor score
Files withINTEL CORP21
This identity is grouped by exact name match (no disambiguated inventor record was available for these filings) — it may combine same-named inventors.
Top patents by PatentIndex Score
21 records- 0159US2026006836A1Integrated circuit structures having differentiated dielectric boundary wallsINTEL CORP·Filed 2024·Application pending·0 cites
- 0258US12563810B1Selective backside recessing of source and drain regionsINTEL CORP·Filed 2023·Granted Feb 24, 2026·0 cites·20 claims
- 0358US2026006871A1Gate-all-around integrated circuit structures having differentiated internal spacersINTEL CORP·Filed 2024·Application pending·0 cites
- 0458US2026006837A1Integrated circuit structure with zero diffusion break and wrap-around contactINTEL CORP·Filed 2024·Application pending·0 cites
- 0558US2026006859A1Strain engineering using gate cutsINTEL CORP·Filed 2024·Application pending·0 cites
- 0658US2026096195A1Cell architecture with forksheet and gate-all-around devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 0758US2026005067A1Backside etch processes for ultra uniformity of front-end structuresINTEL CORP·Filed 2024·Application pending·0 cites
- 0858US2026006838A1Fabrication of gate-all-around integrated circuit structures having selectively grown metal gate structuresINTEL CORP·Filed 2024·Application pending·0 cites
- 0958US2026090023A1Defect-free epitaxial source and drain structures for ribbon field effect transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 1058US2026090025A1Gate-all-around integrated circuit structures having differentiated release layersINTEL CORP·Filed 2024·Application pending·0 cites
- 1158US2026006873A1Fabrication of ribbon cfets with optimized nmos and pmos channel materialsINTEL CORP·Filed 2024·Application pending·0 cites
- 1258US2026090039A1Improved removal of sacrificial material for minimized channel extensionsINTEL CORP·Filed 2024·Application pending·0 cites
- 1358US2026090024A1Complementary gate cut plugs for strain optimizationINTEL CORP·Filed 2024·Application pending·0 cites
- 1456US2026006842A1Self-aligned fork-last backbone for forksheet transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 1556US2026006846A1Sacrificial ribbon for uniform workfunction and capacitance benefitsINTEL CORP·Filed 2024·Application pending·0 cites
- 1656US2026006906A1Silicon source and drain trench fill for wider contactsINTEL CORP·Filed 2024·Application pending·0 cites
- 1756US2026032960A1Backside contact structure with enhanced ohmic contactINTEL CORP·Filed 2024·Application pending·0 cites
- 1856US2026006860A1Integrated circuit structures having stress-inducing gate cut plugsINTEL CORP·Filed 2024·Application pending·0 cites
- 1956US2026006833A1Transistor metallization endcap scaling for performance optimizationINTEL CORP·Filed 2024·Application pending·0 cites
- 2048US12543367B2Backside processing of fins in fin based transistor devicesINTEL CORP·Filed 2022·Granted Feb 3, 2026·0 cites·25 claims
- 2142US12568643B2Nanowire transistors and methods of fabricationINTEL CORP·Filed 2020·Granted Mar 3, 2026·0 cites·14 claims
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Identity basis: exact name match across USPTO filings. How scoring works →