Self-aligned fork-last backbone for forksheet transistors

Abstract

Embodiments disclosed herein include forksheet transistor transistors with self-aligned fork-last backbones. In an example, an integrated circuit structure includes a dielectric backbone. A first vertical stack of nanowires is laterally adjacent to and in contact with a first side of the dielectric backbone. A first epitaxial source or drain structure is at an end of the first vertical stack of nanowires. A second vertical stack of nanowires is laterally adjacent to and in contact with a second side of the backbone, the second side laterally opposite the first side. A second epitaxial source or drain structure is at an end of the second vertical stack of nanowires, the second epitaxial source or drain structure laterally adjacent to but not merged with the first epitaxial source or drain structure.

What is claimed is: 
     
         1 . An integrated circuit structure, comprising:
 a dielectric backbone;   a first vertical stack of nanowires laterally adjacent to and in contact with a first side of the dielectric backbone;   a first epitaxial source or drain structure at an end of the first vertical stack of nanowires;   a second vertical stack of nanowires laterally adjacent to and in contact with a second side of the backbone, the second side laterally opposite the first side; and   a second epitaxial source or drain structure at an end of the second vertical stack of nanowires, the second epitaxial source or drain structure laterally adjacent to but not merged with the first epitaxial source or drain structure.   
     
     
         2 . The integrated circuit structure of  claim 1 , further comprising:
 a dielectric liner on a top and along sides of the first epitaxial source or drain structure, the dielectric liner intervening between the first epitaxial source or drain structure and the second epitaxial source or drain structure.   
     
     
         3 . The integrated circuit structure of  claim 1 , further comprising:
 a dielectric spacer along a side but not on a top of the first epitaxial source or drain structure, the dielectric spacer intervening between the first epitaxial source or drain structure and the second epitaxial source or drain structure.   
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the first epitaxial source or drain structure is a P-type epitaxial source or drain structure. 
     
     
         5 . The integrated circuit structure of  claim 4 , wherein the second epitaxial source or drain structure is an N-type epitaxial source or drain structure. 
     
     
         6 . An integrated circuit structure, comprising:
 a dielectric backbone;   a first vertical stack of nanowires and a first dielectric cap laterally adjacent to and in contact with a first side of the dielectric backbone;   a first gate electrode around the first vertical stack of nanowires and the first dielectric cap, the first gate electrode in contact with the first side of the dielectric backbone;   a second vertical stack of nanowires and a second dielectric cap laterally adjacent to and in contact with a second side of the backbone, the second side laterally opposite the first side; and   a second gate electrode around the second vertical stack of nanowires and the second dielectric cap, the second gate electrode in contact with the second side of the dielectric backbone.   
     
     
         7 . The integrated circuit structure of  claim 6 , wherein an upper portion of the dielectric backbone has a wider width than a lower portion of the dielectric backbone. 
     
     
         8 . The integrated circuit structure of  claim 6 , wherein an upper portion of the dielectric backbone is on a portion of a top surface of the first dielectric cap. 
     
     
         9 . The integrated circuit structure of  claim 8 , wherein the upper portion of the dielectric backbone is on a portion of a top surface of the second dielectric cap. 
     
     
         10 . The integrated circuit structure of  claim 6 , wherein the first vertical stack of nanowires is above a first sub-fin structure, and the second vertical stack of nanowires is above a second sub-fin structure. 
     
     
         11 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising:
 a dielectric backbone; 
 a first vertical stack of nanowires laterally adjacent to and in contact with a first side of the dielectric backbone; 
 a first epitaxial source or drain structure at an end of the first vertical stack of nanowires; 
 a second vertical stack of nanowires laterally adjacent to and in contact with a second side of the backbone, the second side laterally opposite the first side; and 
 a second epitaxial source or drain structure at an end of the second vertical stack of nanowires, the second epitaxial source or drain structure laterally adjacent to but not merged with the first epitaxial source or drain structure. 
   
     
     
         12 . The computing device of  claim 11 , wherein the integrated circuit structure further comprises a dielectric liner on a top and along sides of the first epitaxial source or drain structure, the dielectric liner intervening between the first epitaxial source or drain structure and the second epitaxial source or drain structure. 
     
     
         13 . The computing device of  claim 11 , wherein the integrated circuit structure further comprises a dielectric liner on a top and along sides of the first epitaxial source or drain structure, the dielectric liner intervening between the first epitaxial source or drain structure and the second epitaxial source or drain structure. 
     
     
         14 . The computing device of  claim 11 , further comprising:
 a memory coupled to the board.   
     
     
         15 . The computing device of  claim 11 , further comprising:
 a communication chip coupled to the board.   
     
     
         16 . The computing device of  claim 11 , further comprising:
 a battery coupled to the board.   
     
     
         17 . The computing device of  claim 11 , further comprising:
 a camera coupled to the board.   
     
     
         18 . The computing device of  claim 11 , further comprising:
 a display coupled to the board.   
     
     
         19 . The computing device of  claim 11 , wherein the component is a packaged integrated circuit die. 
     
     
         20 . The computing device of  claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.