Inventor · name-matched record
MURTHY ANAND S
14 granted patents·9 pending applications·0 citations·filing 2017–2025
81Inventor score
Files withINTEL CORP23
This identity is grouped by exact name match (no disambiguated inventor record was available for these filings) — it may combine same-named inventors.
Top patents by PatentIndex Score
23 records- 0184US2026026096A1Integrated circuit structures having ultra-high conductivity global routingINTEL CORP·Filed 2025·Application pending·0 cites
- 0281US2026026039A1Gate-all-around integrated circuit structures having source or drain structures with regrown central portionsINTEL CORP·Filed 2025·Application pending·0 cites
- 0367US12520482B2Memory arrays with backside components and angled transistorsINTEL CORP·Filed 2023·Granted Jan 6, 2026·0 cites·20 claims
- 0465US12588485B2Integrated circuit structures having airgaps for backside signal routing or power deliveryINTEL CORP·Filed 2022·Granted Mar 24, 2026·0 cites·20 claims
- 0565US12525295B2Two transistor memory cells with angled transistorsINTEL CORP·Filed 2023·Granted Jan 13, 2026·0 cites·20 claims
- 0662US12563724B2Two transistor memory cells with source-drain coupling in one transistorINTEL CORP·Filed 2022·Granted Feb 24, 2026·0 cites·20 claims
- 0759US2026006836A1Integrated circuit structures having differentiated dielectric boundary wallsINTEL CORP·Filed 2024·Application pending·0 cites
- 0858US12588189B2Memory devices with vertical transistorsINTEL CORP·Filed 2022·Granted Mar 24, 2026·0 cites·10 claims
- 0958US12527026B2Field-effect transistor with hybrid switching mechanismINTEL CORP·Filed 2022·Granted Jan 13, 2026·0 cites·19 claims
- 1058US12527078B2Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolationINTEL CORP·Filed 2021·Granted Jan 13, 2026·0 cites·10 claims
- 1158US2026006871A1Gate-all-around integrated circuit structures having differentiated internal spacersINTEL CORP·Filed 2024·Application pending·0 cites
- 1258US2026006837A1Integrated circuit structure with zero diffusion break and wrap-around contactINTEL CORP·Filed 2024·Application pending·0 cites
- 1358US2026006838A1Fabrication of gate-all-around integrated circuit structures having selectively grown metal gate structuresINTEL CORP·Filed 2024·Application pending·0 cites
- 1458US2026090025A1Gate-all-around integrated circuit structures having differentiated release layersINTEL CORP·Filed 2024·Application pending·0 cites
- 1556US12520573B2SiGe:GAB source or drain structures with low resistivityINTEL CORP·Filed 2022·Granted Jan 6, 2026·0 cites·25 claims
- 1656US2026006842A1Self-aligned fork-last backbone for forksheet transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 1756US2026006860A1Integrated circuit structures having stress-inducing gate cut plugsINTEL CORP·Filed 2024·Application pending·0 cites
- 1855US12575401B2Integrated circuit devices with angled transistors and angled routing tracksINTEL CORP·Filed 2023·Granted Mar 10, 2026·0 cites·20 claims
- 1954US12575170B2Low temperature, high germanium, high boron SiGe:B pEPI with a silicon rich capping layer for ultra-low PMOS contact resistivity and thermal stabilityINTEL CORP·Filed 2021·Granted Mar 10, 2026·0 cites·17 claims
- 2054US12575151B2Gate-all-around integrated circuit structures having doped subfinINTEL CORP·Filed 2021·Granted Mar 10, 2026·0 cites·20 claims
- 2153US12598777B2Low temperature, high germanium, high boron SiGe:B pEPI with titanium silicide contacts for ultra-low PMOS contact resistivity and thermal stabilityINTEL CORP·Filed 2021·Granted Apr 7, 2026·0 cites·14 claims
- 2253US12593486B2Dual contact process with selective depositionINTEL CORP·Filed 2020·Granted Mar 31, 2026·0 cites·17 claims
- 2341US12550401B2Doped STI to reduce source/drain diffusion for germanium NMOS transistorsINTEL CORP·Filed 2017·Granted Feb 10, 2026·0 cites·22 claims
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Identity basis: exact name match across USPTO filings. How scoring works →