Inter-fan-out wafer level packaging with coaxial TIV for 3D IC low-noise packaging

Abstract

A semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor element includes at least one conductive layer and at least one via layer. The insulating layer is positioned above the first semiconductor device and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The at least one TIV has a conductive core including a copper-containing material. The second semiconductor element is positioned above the insulating layer and includes at least one conductive layer and at least one via layer. The at least one TIV couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element.

What is claimed is: 
     
       1. A semiconductor package comprising,
 a first semiconductor element comprising at least one conductive layer and at least one via layer; 
 an insulating layer positioned above the first semiconductor element, the insulating layer comprising at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer, wherein the TIV comprises a conductive core including a copper-containing material; and 
 a second semiconductor element comprising at least one conductive layer and at least one via layer, wherein the second semiconductor element is positioned above the insulating layer, and 
 wherein the at least one TIV couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element, wherein the at least one TIV comprises a first insulating layer disposed around the conductive core and a ground shielding layer disposed around the first insulating layer. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein the ground shielding layer comprises a copper-containing material. 
     
     
       3. The semiconductor package of  claim 1 , wherein the insulating layer comprises a low temperature plasma enhanced chemical vapor deposition (PECVD) dielectric. 
     
     
       4. The semiconductor package of  claim 3 , wherein PECVD dielectric comprises a silicon-based dielectric. 
     
     
       5. The semiconductor package of  claim 1 , comprising a second insulating layer disposed around the ground shielding layer. 
     
     
       6. The semiconductor package of  claim 5 , wherein the second insulating layer comprises a polymer insulating material selected from the group consisting of polybenzoxazole (PBO), polyimide (PI), and benzocyclobutene (BCB). 
     
     
       7. The semiconductor package of  claim 1 , wherein the copper-containing material comprises a titanium/copper (Ti/Cu) material. 
     
     
       8. The semiconductor package of  claim 1 , wherein the insulating layer comprises an interposer including one or more active semiconductor devices. 
     
     
       9. A method of forming the semiconductor package of  claim 1 , comprising:
 forming a first conductive layer on a substrate, wherein the first conductive layer comprises at least one conductive trace; 
 forming an insulating layer above the first conductive layer, wherein the insulating layer includes at least one through insulating via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer, and wherein the TIV comprises a conductive core coupled to the at least one conductive trace of the first conductive layer; 
 forming a via layer above the insulating layer, wherein the via layer comprises at least one conductive via extending from a first side to a second side of the via layer, and wherein the at least one conductive via is coupled to the at least one TIV of the insulating layer; and 
 forming a second conductive layer above the via layer, wherein the second conductive layer comprises at least one conductive trace coupled to the at least one conductive via of the via layer. 
 
     
     
       10. The method of  claim 9 , wherein forming the insulating layer comprises:
 depositing a TIV hole photoresist layer over the first via layer, wherein the TIV hole photoresist layer defines at least one TIV hole positioned at least partially above the at least one conductive via of the first via layer; 
 depositing a first conductive copper-containing material over the TIV hole photoresist layer, wherein the first conductive copper-containing material is deposited to a depth sufficient to fill the at least one TIV hole; and 
 removing the TIV hole photoresist layer such that a column of the first conductive copper-containing material defines a conductive core of the at least one TIV. 
 
     
     
       11. The method of  claim 10 , wherein forming the insulating layer further comprises:
 depositing a first insulating layer over the column of the first conductive copper-containing material; and 
 depositing a second conductive copper-containing material over the first insulating layer, wherein the column of the first conductive copper-containing material, the first insulating layer, and the second conductive copper-containing material define the at least one TIV. 
 
     
     
       12. The method of  claim 11 , wherein depositing the first insulating layer comprises depositing a low temperature plasma enhanced chemical vapor deposition (PECVD) dielectric material. 
     
     
       13. The method of  claim 11 , wherein forming the insulating layer comprises performing a planarizing operation to expose the conductive core. 
     
     
       14. The method of  claim 11 , comprising forming a second insulating layer over the at least one TIV. 
     
     
       15. The method of  claim 14 , wherein the second insulating layer comprises a material selected from the group consisting of polybenzoxazole (PBO), polyimide (PI), and benzocyclobutene (BCB). 
     
     
       16. The method of  claim 9 , comprising coupling at least one active semiconductor die to the insulating layer. 
     
     
       17. The method of  claim 9 , comprising:
 forming a connection pad above the second conductive layer, wherein the connection pad is coupled to the at least one conducive trace formed in the second conductive layer; and 
 forming a solder ball over the connection pad. 
 
     
     
       18. A semiconductor package, comprising:
 a first semiconductor element comprising:
 a first conductive layer including at least one conductive trace; and 
 a first via layer including at least one conductive via coupled to the at least one conductive trace of the first conductive layer; 
 
 an insulating layer positioned above the first semiconductor element, the insulating layer comprising:
 an active semiconductor device; 
 a through insulating via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer, wherein the TIV comprises a conductive core, an insulating layer at least partially around the conductive core, and a ground-shielding layer at least partially around the insulating layer, wherein the conductive core is coupled to the at least one conductive via of the first via layer at a first end of the TIV, wherein the conductive core and the ground-shielding layer each comprise a copper-including material; and 
 an insulating material positioned between the active semiconductor device and the TIV; and 
 
 a second semiconductor element positioned above the insulating layer, the second semiconductor element comprising:
 a second via layer including at least one conductive via coupled to the conductive core of the TIV at a second end of the TIV; and 
 a second conductive layer including at least one conductive trace coupled to the at least one conductive via of the second via layer. 
 
 
     
     
       19. The semiconductor package of  claim 18 , wherein the first copper containing material is a titanium-copper material.