Stacked multilayer structure and manufacturing method thereof

Abstract

A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

What is claimed is: 
     
       1. A memory device comprising:
 a substrate; 
 a first wiring extending in a first direction parallel to a surface of the substrate; 
 a second wiring provided above the first wiring; 
 a third wiring provided between the first wiring and the second wiring in a second direction, the second direction being perpendicular to the surface of the substrate; 
 a fourth wiring extending in the second direction; 
 a first variable resistivity portion provided between the second wiring and the fourth wiring; 
 a second variable resistivity portion provided between the third wiring and the fourth wiring; and 
 a first vertical transistor provided between the first wiring and the fourth wiring. 
 
     
     
       2. The memory device according to  claim 1 , further comprising a fifth wiring extending in a third direction, the third direction being perpendicular to the second direction and crossing the first direction,
 wherein a gate of the first vertical transistor is connected to the fifth wiring. 
 
     
     
       3. The memory device according to  claim 1 , wherein the first variable resistivity portion includes a variable resistivity element and a diode. 
     
     
       4. The memory device according to  claim 3 , wherein the first variable resistivity portion includes a metal silicide film between the variable resistivity element and the diode. 
     
     
       5. The memory device according to  claim 3 , wherein the diode is provided between the variable resistivity element and the second wiring. 
     
     
       6. The memory device according to  claim 1 , wherein the first wiring is an N type polysilicon film. 
     
     
       7. The memory device according to  claim 1 , wherein the first variable resistivity portion includes an oxide transition metal film. 
     
     
       8. The memory device according to  claim 1 , wherein the first variable resistivity portion includes a metal oxide film. 
     
     
       9. The memory device according to  claim 1 , wherein the first variable resistivity portion includes a nickel oxide film. 
     
     
       10. The memory device according to  claim 1 , wherein the fourth wiring is a metal. 
     
     
       11. The memory device according to  claim 1 , wherein the fourth wiring includes titanium nitride. 
     
     
       12. The memory device according to  claim 1 , wherein the first wiring is a metal, the first wiring being provided on the substrate via an insulating film. 
     
     
       13. The memory device according to  claim 12 , wherein the first wiring is tungsten. 
     
     
       14. The memory device according to  claim 1 , wherein the first vertical transistor has an N type semiconductor layer extending in the second direction. 
     
     
       15. The memory device according to  claim 2 , wherein the fifth wiring includes a P type semiconductor. 
     
     
       16. The memory device according to  claim 1 , wherein the first resistance change portion includes a phase change element. 
     
     
       17. The memory device according to  claim 16 , wherein the phase change element includes chalcogenide. 
     
     
       18. The memory device according to  claim 1 , further comprising:
 a first selection transistor electrically connected to the second wiring; and 
 a second selection transistor electrically connected to the third wiring. 
 
     
     
       19. The memory device according to  claim 1 , further comprising:
 a sixth wiring extending in the second direction, the fourth wiring and the sixth wiring being arranged in the first direction; and 
 a second vertical transistor provided between the first wiring and the sixth wiring. 
 
     
     
       20. The memory device according to  claim 19 , further comprising a seventh wiring extending in the third direction,
 wherein a gate of the second vertical transistor is connected to the seventh wiring. 
 
     
     
       21. The memory device according to  claim 19 , further comprising:
 a third variable resistivity portion provided between the second wiring and the sixth wiring; and 
 a fourth variable resistivity portion provided between the third wiring and the sixth wiring.