US10078101B2ActiveUtilityA1

Wafer level integrated circuit probe array and method of construction

86
Assignee: JOHNSTECH INT CORPPriority: Apr 21, 2009Filed: Mar 10, 2015Granted: Sep 18, 2018
Est. expiryApr 21, 2029(~2.8 yrs left)· nominal 20-yr term from priority
G01R 3/00G01R 1/07314G01R 1/06738G01R 1/07371G01R 1/06733G01R 1/06772
86
PatentIndex Score
4
Cited by
29
References
8
Claims

Abstract

A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). To prevent rotation of the pins in the pin guide, a walled recess in the bottom of the pin guide engages flanges on the pins. In another embodiment, the pin guide maintains rotational alignment by being fitted around the pin profile or having projections abutting the pin. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.

Claims

exact text as granted — not AI-modified
The invention claimed is: 
     
       1. A test contact pin assembly for temporary contact with an integrated circuit device under test (DUT) comprising:
 a. at least one slideable upper terminal pin, having, a top extension for contacting the DUT, at least one lateral cross member flange and a contact surface; said upper pin being slideable between an out of test position and an in-test position; 
 b. at least one lower terminal pin having a foot and a like contact surface; 
 c. said upper and lower pins being held in contact by bias forces which maintain their respective contacts surfaces together but in a slideable relationship to each other; 
 d. an elastomeric material of predetermined height when in an uncompressed state, said material surrounding at least a portion of the pins to create said bias force on the pins; and 
 e. a rigid anti-intrusion layer interposed between said flange and said elastomeric material, to prevent the elastomeric material from being deformed by said flange. 
 
     
     
       2. A test contact pin assembly for temporary contact with an integrated circuit device under test (DUT) comprising:
 a. a pin guide having a plurality of apertures for receiving terminal contact pins; 
 b. upper terminal pins, each slideable within said pin guide and having a top extension for contacting the DUT and at least one planar sidewall along said extension, said upper pin being slideable between an out of test position and an in-test position; 
 c. lower terminal pins, each having at least one planar sidewall, and a contact surface for contacting a load board; 
 d. said upper and lower pins being held in contact by bias forces which maintain their respective contacts surfaces together but in a slideable relationship to each other; 
 e. an anti-rotation plate having a plurality of apertures corresponding with and in axial alignment with said apertures on said pin guide, so that said pins pass through both sets of apertures, and wherein said anti-rotation plate further includes a bias element applied to the pin passing therethrough to prevent rotation of said pin when contacting the DUT. 
 
     
     
       3. The pin assembly of  claim 2  further including:
 an elastomeric material of predetermined height when in an uncompressed state, said material surrounding at least a portion of the pins to create said bias force on the pins to maintain said planar side walls in contact with each other when the pins slide relative to each other. 
 
     
     
       4. The pin assembly of  claim 2  wherein said bias element includes a plurality of projection tabs extending from inner sidewalls of said anti-rotation plate apertures to slideably contact said pin. 
     
     
       5. The pin assembly of  claim 2  wherein said bias element includes a scored surface covering apertures and wherein said pins rupture said scored surface when inserted thereby creating plurality of projection tabs extending from inner sidewalls of said anti-rotation plate apertures to slideably contact said pin. 
     
     
       6. The pin assembly of  claim 2  wherein said bias element includes projecting contact surfaces projecting from said apertures into the spaced defined by said apertures and further including a pressure reliever capable of relieving some of the pressure created by engagement of the said contact surfaces against said pins. 
     
     
       7. The pin assembly of  claim 6  wherein said pressure reliever includes slots in said anti-rotation plate adjacent said apertures. 
     
     
       8. A test contact pin assembly for temporary contact with a test pad on a wafer level integrated circuit device under test (DUT) comprising:
 a. at least one slideable upper terminal pin, further having, a top extension for contacting the DUT, portion, at least one lateral cross member flange and a contact surface; said upper pin being slideable between an out of test position and an in-test position; 
 b. at least one lower terminal pin having a foot and a like contact surface; 
 c. said upper and lower pins being held in contact by bias forces which maintain their respective contacts surfaces together but in a slideable relationship to each other; 
 d. an elastomeric material of predetermined height when in an uncompressed state, said material surrounding the pins to create said bias force; 
 e. a rigid top pin guide surface located atop said elastomeric material, including apertures for receiving the pins 
 f. a layer applied on top of said guide surface including a cross cut aperture thereby freeing a plurality of flaps which extend along and engage said pin, providing a bias force against the pin in both x and y axes, thereby tending to prevent rotation of the pin; 
 g. an upper wall between said parallel walls defining an up-stop surface for said pin and an aperture in said up-stop surface for receiving an extended portion of said upper pin which protrudes beyond said guide surface to make contact with said DUT, said channel being sized to be large enough to receive said flange with minimum frictional contact the parallel walls; said up-stop surface providing an upward stop limit for the upper pin by virtue of its contact with the flange.

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