Stacked type semiconductor memory device and method for manufacturing the same

Abstract

According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a substrate comprising a cell source line; 
 a first bit line extending in a first direction, the first direction being parallel to an upper surface of the substrate; 
 a first signal line extending in a second direction crossing the first direction and the upper surface of the substrate, the first signal line having a first portion contacting the cell source line at an end of the first signal line, 
 a first select transistor being electrically connected to the first bit line and the first signal line; 
 a second signal line being arranged apart from and adjacent to the first signal line in the first direction, the second signal line extending in the second direction, the second signal line having a second portion contacting the cell source line at an end of the second signal line in the second direction; 
 a second select transistor being electrically connected to the first bit line and the second signal line; 
 a first insulator disposed between the first signal line and the second signal line; 
 a first gate electrode extending in a third direction crossing the first and the second directions; 
 a second gate electrode extending in the third direction, the first signal line and the second signal line being disposed between the first gate electrode and the second gate electrode in the first direction; 
 a first memory cell between the first signal line and the first gate electrode to store first information by applying voltage between the first signal line and the first gate electrode; 
 a second memory cell between the second signal line and the second gate electrode to store second information by applying voltage between the second signal line and the second gate electrode; 
 a third signal line being arranged apart from the second signal line in the first direction, the third signal line extending in the second direction, the third signal line having a third portion contacting the cell source line at an end of the third signal line in the second direction; 
 a third select transistor being electrically connected to the first bit line and the third signal line; 
 a fourth signal line being arranged apart from the third signal line in the first direction, the fourth signal line extending in the second direction, the fourth signal line having a fourth portion contacting the cell source line at an end of the fourth signal line in the second direction; 
 a fourth select transistor being electrically connected to the first bit line and the fourth signal line; 
 a second insulator disposed between the third signal line and fourth signal line; 
 a third gate electrode extending in the third direction, the second gate electrode and the third gate electrode being disposed between the second signal line and the third signal line in the first direction; 
 a fourth gate electrode extending in the third direction, the first gate electrode being electrically connected to one of the third gate electrode and the fourth gate electrode, and the second gate electrode being electrically connected to the other one of the third gate electrode and the fourth gate electrode; 
 a third insulator disposed between the second gate electrode and the third gate electrode; 
 a third memory cell between the third signal line and the third gate electrode to store third information by applying voltage between the third signal line and the third gate electrode; and 
 a fourth memory cell between the fourth signal line and the fourth gate electrode to store fourth information by applying voltage between the fourth signal line and the fourth gate electrode, 
 wherein the first portion and the second portion face each other in the first direction and contact each other beneath the first insulator and above the cell source line in the second direction, the first portion is dented in the first direction from an upper part of the first signal line and the second portion is dented in the first direction from an upper part of the second signal line. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , further comprising:
 a first contact electrically connected to the first select transistor; and 
 a second contact electrically connected to the second select transistor. 
 
     
     
       3. The semiconductor memory device according to  claim 2 , wherein the first contact and the second contact are next to each other in the first direction. 
     
     
       4. The semiconductor memory device according to  claim 2 , further comprising:
 a fifth select transistor provided directly above the second select transistor in the second direction; and 
 a third contact electrically connected to the fifth select transistor, the third contact being shorter than the second contact in the second direction. 
 
     
     
       5. The semiconductor memory device according to  claim 2 , further comprising:
 a fourth contact electrically connected to the first gate electrode, the fourth contact being longer than both of the first and the second contact in the second direction. 
 
     
     
       6. The semiconductor memory device according to  claim 1 , wherein a space between the second gate electrode and the third gate electrode is free from semiconductor. 
     
     
       7. The semiconductor memory device according to  claim 1 , wherein the first gate electrode, the first memory cell, the first signal line, the first insulator, the second memory cell, the second signal line, the third insulator, the third gate electrode, the third memory cell, the third signal line, the second insulator, the fourth memory cell, and the fourth signal line exist along the first direction in this order. 
     
     
       8. The semiconductor memory device according to  claim 1 , wherein the third portion and the fourth portion face each other in the first direction and contact each other beneath the second insulator and above the cell source line in the second direction, the third portion is dented in the first direction from an upper part of the third signal line, and the fourth portion is dented in the first direction from an upper part of the fourth signal line.