Interconnect structure and methods of making same

Abstract

A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the low-k dielectric layer, where the opening exposes a portion of the substrate. The method may also include filling the opening with a copper alloy and forming a copper-containing layer over the copper alloy and the low-k dielectric layer. An etch rate of the copper-containing layer may be greater than an etch rate of the copper alloy. The method may additionally include patterning the copper-containing layer to form interconnect features over the low-k dielectric layer and the copper alloy.

What is claimed is: 
     
       1. A semiconductor interconnect structure comprising:
 a dielectric layer on a substrate; 
 a copper alloy feature extending substantially vertically into the dielectric layer, the copper alloy feature having a first etch rate; and 
 a plurality of copper-containing interconnect features on the dielectric layer and the copper alloy feature, wherein the copper-containing interconnect features comprise from about 98% to about 100% copper and have a second etch rate, the second etch rate being greater than the first etch rate relative a same etch process. 
 
     
     
       2. The semiconductor interconnect structure of  claim 1 , wherein the copper alloy feature comprises a material selected from the group consisting essentially of CuMn, CuCr, CuV, CuNb, CuTi, and combinations thereof. 
     
     
       3. The semiconductor interconnect structure of  claim 1 , wherein an etch selectivity of the plurality of copper-containing interconnect feature relative to the copper alloy feature is at least 5:1. 
     
     
       4. The semiconductor interconnect structure of  claim 1  further comprising a hard mask disposed between the plurality of copper-containing interconnect features and the dielectric layer along a line perpendicular to a major surface of the substrate. 
     
     
       5. The semiconductor interconnect structure of  claim 1  further comprising an etch stop layer under the dielectric layer, wherein the copper alloy feature extends through the etch stop layer. 
     
     
       6. The semiconductor interconnect structure of  claim 1 , wherein a density of the copper alloy feature is greater than a conductive feature having a same material composition as the copper alloy feature immediately after a deposition process. 
     
     
       7. A device comprising:
 a low-k dielectric layer over a semiconductor substrate; 
 a copper alloy feature extending through the low-k dielectric layer; and 
 a copper-containing conductive line over the low-k dielectric layer and the copper alloy feature, wherein the copper-containing conductive line comprises substantially pure copper, and wherein the copper-containing conductive line has an etching rate greater than an etching rate of the copper alloy feature relative a same etch process. 
 
     
     
       8. The device of  claim 7 , wherein the copper-containing conductive line is in direct contact with the copper alloy feature. 
     
     
       9. The device of  claim 7 , wherein the copper-containing conductive line comprises about 98% to about 100% copper. 
     
     
       10. The device of  claim 7 , wherein the copper alloy feature comprises CuMn, CuCr, CuV, CuNb, CuTi, or a combination thereof. 
     
     
       11. The device of  claim 7  further comprising an etch stop layer disposed between the low-k dielectric layer and the semiconductor substrate, wherein the copper alloy feature extends through the etch stop layer. 
     
     
       12. The device of  claim 7 , further comprising a hard mask disposed between the low-k dielectric layer and the copper-containing conductive line, wherein the copper alloy feature extends through the hard mask. 
     
     
       13. The device of  claim 7 , wherein an etch selectivity of the copper-containing conductive line relative to the copper alloy feature is at least 5:1 relative a same etch process. 
     
     
       14. The device of  claim 7 , wherein the copper alloy feature extends laterally past a sidewall of the copper-containing conductive line. 
     
     
       15. A device comprising:
 a semiconductor substrate having an active device formed at a top surface; 
 a low-k dielectric layer over the top surface of the semiconductor substrate; 
 a conductive via extending through the low-k dielectric layer, wherein the conductive via comprises a combination of copper and a material different from copper; 
 a hard mask over the low-k dielectric layer, wherein the conductive via extends through the hard mask; 
 a second dielectric layer over the conductive via and the hard mask, wherein the second dielectric layer forms a first interface with a top surface of the conductive via; and 
 a conductive line in the second dielectric layer, wherein a bottom surface of the conductive line forms a second interface with the conductive via and a third interface with the hard mask, wherein the conductive line comprises copper, and wherein a copper percentage of the conductive line is greater than a copper percentage of the conductive via. 
 
     
     
       16. The device of  claim 15 , wherein a first etch selectivity of the conductive line is lower than a second etch selectivity of the conductive via relative a same etching process. 
     
     
       17. The device of  claim 15 , wherein the material different from copper is selected from the group consisting essentially of Mn, Cr, V, Nb, Ti, and combinations thereof. 
     
     
       18. The device of  claim 15 , wherein the conductive line comprises about 98% to about 100% copper. 
     
     
       19. The device of  claim 15 , wherein the conductive via comprises about 90% to about 99.8% copper.