Method of manufacturing semiconductor device using a plurality of etch stop layers

Abstract

A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device, the method comprising:
 providing a first interlayer dielectric layer having a conductive pattern; 
 sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer; 
 forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing a top surface of the second etch stop layer; and 
 performing an etching process in a single etch, the single etch including removing the mask pattern and the second etch stop layer exposed by the opening to expose a top surface of the first etch stop layer. 
 
     
     
       2. The method of  claim 1 , wherein the performing does not expose the conductive pattern. 
     
     
       3. The method of  claim 1 , further comprising:
 exposing the conductive pattern by removing the first etch stop layer exposed by the opening; 
 forming a conductive layer in the opening and on the second interlayer dielectric layer; and 
 planarizing the conductive layer to expose an upper surface of the second interlayer dielectric layer. 
 
     
     
       4. The method of  claim 3 , wherein the removing the mask pattern removes the mask pattern before the forming a conductive layer. 
     
     
       5. The method of  claim 3 , wherein a portion of the first etch stop layer and a portion of the second etch stop layer remain between the conductive pattern and the second interlayer dielectric layer after the exposing the conductive pattern. 
     
     
       6. The method of  claim 1 , wherein the sequentially forming forms the first etch stop layer including silicon (Si) and carbon (C). 
     
     
       7. The method of  claim 1 , wherein the sequentially forming forms the second etch stop layer including an insulating layer containing aluminum (Al). 
     
     
       8. The method of  claim 1 , wherein the sequentially forming forms the mask pattern including at least one of titanium oxide, titanium nitride, tungsten, and any combination thereof. 
     
     
       9. The method of  claim 1 , further comprising:
 forming a capping layer between the second interlayer dielectric layer and the mask pattern. 
 
     
     
       10. A method of manufacturing a semiconductor device, the method comprising:
 providing a first interlayer dielectric layer having a first conductive pattern; 
 forming a first etch stop layer on the first conductive pattern and on the first interlayer dielectric layer; 
 forming a second etch stop layer on the first etch stop layer; 
 forming a second interlayer dielectric layer on the second etch stop layer; 
 forming a mask pattern on the second interlayer dielectric layer; 
 forming an opening including a via hole and a trench connected to the via hole in the second interlayer dielectric layer to expose the second etch stop layer by etching the second interlayer dielectric layer not covered with the mask pattern, 
 wherein the trench has a width greater than that of the via hole; and 
 removing the mask pattern to expose a topmost surface of the second interlayer dielectric layer and remove the second etch stop layer, 
 wherein the first etch stop layer has a portion overlapped with the via hole in a plan view, and 
 wherein the portion of the first etch stop layer is covered by the second etch stop layer after formation of the opening. 
 
     
     
       11. The method of  claim 10 , wherein the removing etches the second etch stop layer to expose the first etch stop layer,
 wherein the first etch stop layer has an etch selectivity with respect to the second etch stop layer during the etching the second etch stop layer. 
 
     
     
       12. The method of  claim 11 , further comprising:
 exposing the first conductive pattern by removing the first etch stop layer exposed by the opening; 
 forming a conductive layer in the opening and on the second interlayer dielectric layer; and 
 planarizing the conductive layer to form a second conductive pattern in the opening. 
 
     
     
       13. The method of  claim 10 , wherein
 the forming a first etch stop layer includes forming at least one of silicon carbide, silicon nitride, silicon carbon nitride, silicon boron carbide, silicon boron carbon nitride, and any combination thereof, and 
 the forming a second etch stop layer includes forming an insulating layer containing aluminum. 
 
     
     
       14. The method of  claim 10 , wherein a sum of thicknesses of the first and second etch stop layers is about 20 angstroms to about 100 angstroms. 
     
     
       15. The method of  claim 10 , wherein the second interlayer dielectric layer has a dielectric constant less than that of the first etch stop layer and the second etch stop layer. 
     
     
       16. The method of  claim 10 , wherein the providing the first interlayer dielectric layer includes providing the first conductive pattern including,
 a metal pattern including one of tungsten and copper, and 
 a barrier metal pattern on a sidewall and a bottom surface of the metal pattern. 
 
     
     
       17. A method of manufacturing a semiconductor device, the method comprising:
 forming a first interlayer dielectric layer on a substrate, the first interlayer dielectric layer having a first conductive pattern; 
 forming a first etch stop layer on the first conductive pattern and on the first interlayer dielectric layer; 
 forming a second etch stop layer on the first etch stop layer; 
 forming a second interlayer dielectric layer on the second etch stop layer; 
 forming a mask pattern on the second interlayer dielectric layer; 
 forming an opening in the second interlayer dielectric layer to expose a top surface of the second etch stop layer by etching the second interlayer dielectric layer not covered with the mask pattern; and 
 removing the second etch stop layer exposed by the opening and the mask pattern to expose an upper surface of the first etch stop layer and an upper surface of the second interlayer dielectric layer, respectively, 
 wherein the first etch stop layer includes silicon (Si) and carbon (C); 
 wherein the second etch stop layer includes an insulating layer containing aluminum (Al); 
 wherein the mask pattern includes titanium or tungsten, and 
 wherein the first etch stop layer comprises a portion overlapped with the opening in a plan view, wherein the portion of the first etch stop remains on the first conductive pattern during the removing the mask pattern. 
 
     
     
       18. The method of  claim 1 , wherein
 the mask includes metal. 
 
     
     
       19. The method of  claim 1 , the opening includes:
 a via hole having a first width in a lower portion of the second interlayer dielectric layer; and 
 a trench having a second width in an upper portion of the second interlayer dielectric layer, the trench connected to the via hole, 
 wherein the second width is greater the first width, 
 wherein the via hole and the trench are formed before performing the etching process. 
 
     
     
       20. The method of  claim 17 , wherein removing the second etch stop layer exposed by the opening and the mask pattern includes simultaneously removing the mask pattern and the second etch stop layer.