Semiconductor packages including stacked chips

Abstract

A semiconductor package may include a first chip stack including first chips which are stacked on a package substrate. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate. The semiconductor package may include a third chip disposed on the first and second chip stacks.

What is claimed is: 
     
       1. A semiconductor package comprising:
 a first chip stack including first chips which are offset from one another and stacked on a package substrate; 
 a second chip stack including second chips which are off set from one another and stacked on the package substrate; 
 a third chip supported by the first and second chip stacks; 
 first bonding wires electrically connecting the first chips to the package substrate; and 
 second bonding wires electrically connecting the second chips to the package substrate, 
 wherein the first bonding wires extend to provide extension portions connecting the first chip stack to the third chip, 
 wherein the third chip is directly electrically connected only to the first chip stack. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein the first chip stack and the second chip stack are disposed to be spaced apart from each other. 
     
     
       3. The semiconductor package of  claim 1 ,
 wherein each of the first chips includes an edge portion on which first chip connection patterns connected to the first bonding wires are disposed; and 
 wherein the first chips are offset to expose the first chip connection patterns. 
 
     
     
       4. The semiconductor package of  claim 1 , wherein a direction in which the first chips are offset is opposite to a direction in which the second chips are offset. 
     
     
       5. The semiconductor package of  claim 1 , wherein the first chip stack has substantially the same height as the second chip stack. 
     
     
       6. The semiconductor package of  claim 1 , wherein the first chips, the second chips, and the third chip have the same function. 
     
     
       7. The semiconductor package of  claim 1 , further comprising a fourth chip disposed between the first and second chip stacks and on the package substrate. 
     
     
       8. The semiconductor package of  claim 1 , further comprising an encapsulant covering the first chip stack, the second chip stack, and the third chip,
 wherein the first chip stack is disposed such that a first forward stepwise sidewall of the first chip stack is adjacent to a first sidewall of the encapsulant, and the second chip stack is disposed such that a second forward stepwise sidewall of the second chip stack is adjacent to a second sidewall of the encapsulant opposite to the first sidewall. 
 
     
     
       9. A semiconductor package comprising:
 a first chip stack including a first reverse stepwise sidewall disposed on a package substrate; 
 a second chip stack including a second reverse stepwise sidewall disposed on the package substrate; and 
 a third chip disposed on the first and second chip stacks, 
 wherein chips of the first and second chip stacks are configured and the first and second chips stacks are positioned on the package substrate so that the second reverse stepwise sidewall faces the first reverse stepwise sidewall, 
 first bonding wires electrically connecting the first chips to the package substrate; and 
 second bonding wires electrically connecting the second chips to the package substrate, 
 wherein the first bonding wires extend to provide extension portions connecting the first chip stack to the third chip, 
 wherein the third chip is directly electrically connected only to the first chip stack. 
 
     
     
       10. The semiconductor package of  claim 9 , wherein at least one chip from the chips of the first and second chip stacks is offset from another chip of the chips of the first and second chip stacks. 
     
     
       11. The semiconductor package of  claim 9 , wherein the third chip is disposed on the first and second chip stacks to prevent the first and second chip stacks from collapsing. 
     
     
       12. The semiconductor package of  claim 9 , further comprising:
 a space between the first and second chip stacks and under the third chip.