III-V semiconductor diode

Abstract

A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n−-layer with a dopant concentration of 1012-1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n−-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n−-layer and the p+-layer and materially bonded with an upper side and a lower side.

What is claimed is: 
     
       1. A stacked III-V semiconductor diode comprising:
 an n + -layer with an upper side, a lower side, a dopant concentration of at least 10 19  N/cm 3  and a layer thickness of about 675 microns or less, wherein said n + -layer comprises a GaAs compound; 
 an n − -layer with an upper side and a lower side, a dopant concentration of 10 12 -10 16  N/cm 3 , a layer thickness of 10-300 microns, and comprising a GaAs compound; 
 a p + -layer with an upper side, a lower side, a dopant concentration of 5×10 18 -5×10 20  N/cm 3 , with a layer thickness greater than 2 microns and comprising a GaAs compound; and 
 a p-type intermediate layer with a layer thickness of 1-50 microns and a dopant concentration of 10 12 -10 17  N/cm 3  is disposed between the n − -layer and the p + -layer, and is materially bonded with an upper side and a lower side, and the lower side of the p-type intermediate layer is materially bonded with the upper side of the n − -layer, and the upper side of the p-type intermediate layer is materially bonded with the lower side of the p + -layer, 
 wherein the n + -layer, the n − -layer, and the p + -layer are monolithically formed, 
 wherein the n + -layer or the p + -layer is formed as a substrate and the lower side of the n − -layer is materially connected to the upper side of the n + -layer, 
 wherein the p-type intermediate layer is materially bonded with the n − -layer and with the p + -layer and is p-doped, 
 wherein the stacked III-V semiconductor diode has a first defect layer with a layer thickness between 0.5 microns and 40 microns, 
 wherein the first defect layer is arranged within the p-type intermediate layer, and 
 wherein the first defect layer has a first defect concentration ranging between 1×10 13  N/cm 3  and 5×10 16  N/cm 3 . 
 
     
     
       2. The III-V semiconductor diode according to  claim 1 , wherein the first defect layer is spaced from the lower side of the p-type intermediate layer by at least half the layer thickness of the p-type intermediate layer. 
     
     
       3. The III-V semiconductor diode according to  claim 1 , wherein the semiconductor diode has a second defect layer, and
 wherein the second defect layer has a layer thickness between 0.5 microns and 40 microns and a second defect concentration between 1×10 13  N/cm 3  and 5×10 16  N/cm 3  and is spaced from the upper side of the p-type intermediate layer by not more than half of the layer thickness of the p-type intermediate layer. 
 
     
     
       4. The III-V semiconductor diode according to  claim 1 , wherein the semiconductor diode has a second defect layer, and
 wherein the first defect layer and/or the second defect layer each comprise a first layer region with the first defect concentration and a second layer region with a second defect concentration. 
 
     
     
       5. The III-V semiconductor diode according to  claim 1 , wherein the semiconductor diode has a second defect layer, and
 wherein the first defect concentration over the layer thickness of the first defect layer and/or a second defect concentration over the layer thickness of the second defect layer occurs according to a random distribution. 
 
     
     
       6. The III-V semiconductor diode according to  claim 1 , wherein the semiconductor diode has a second defect layer, and
 wherein the first defect layer and/or the second defect layer comprises Cr and/or indium and/or aluminum. 
 
     
     
       7. The III-V semiconductor diode according to  claim 1 , wherein a total height of a stacked layer structure formed of the p + -layer, the n − -layer, the p-type intermediate layer and the n + -layer is at most 150-800 microns. 
     
     
       8. The III-V semiconductor diode according to  claim 1 , wherein the stacked layer structure formed of the p + -layer, the n − -layer, the p-type intermediate layer and the n + -layer has a rectangular or square surface with edge lengths between 1 mm and 10 mm. 
     
     
       9. The III-V semiconductor diode according to  claim 1 , wherein the stacked layer structure formed of the p + -layer, the n − -layer, the p-type intermediate layer and the n + -layer has a round or oval or circular surface. 
     
     
       10. The III-V semiconductor diode according to  claim 1 , wherein the p + -layer of the semiconductor diode is replaced by a connection contact layer, and
 wherein the connection contact layer comprises a metal or a metallic compound or comprises essentially of a metal or a metallic compound and forms a Schottky contact. 
 
     
     
       11. The III-V semiconductor diode according to  claim 1 , wherein the III-V semiconductor diode is monolithic or has a semiconductor bond. 
     
     
       12. The III-V semiconductor diode according to  claim 11 , wherein the p-type intermediate layer has a p − -layer, and
 wherein the semiconductor bond is formed between the p − -layer and the n − -layer. 
 
     
     
       13. The III-V semiconductor diode according to  claim 1 , wherein n+-layer, the n−-layer or the p+-layer comprises essentially of the GaAs compound.